I/O Module Timestamping for Signal-Safe Data Transmission

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Solution Overview

Problem

Existing systems for data transmission between signal-safe processing units are complex and costly, with security protocols and clocks integrated within the main computer, leading to delays and reduced precision in timestamping and synchronization.

Innovation Solution

An input and output module with a protocol machine and secure clock is introduced, hard-coded with instructions for clock processing and protocol execution, allowing for secure data transmission and timestamping directly at the hardware level, reducing integration costs and enhancing precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If security protocols and clocks are integrated within the main computer, then signal integrity is ensured, but system complexity and cost increase

Engineering Contradiction:
Improvesignal integrityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the system into two distinct modules: a signal-safe main computer that executes security protocols and generates timestamps, and a separate input/output module that performs timestamping and data transmission. This segmentation allows the main computer to focus on security-critical functions while the I/O module handles peripheral operations, reducing overall system complexity without compromising signal integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The timestamping function is extracted from the main computer and implemented as a dedicated hardware component within the input/output module. This extraction eliminates the need for software-based timestamping in the main computer, reducing its computational burden and complexity while maintaining precise timestamp generation at the I/O level.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If security protocols and clocks are integrated within the main computer, then signal integrity is ensured, but timestamping precision and synchronization are reduced

Engineering Contradiction:
Improvesignal integrityVSAvoidtimestamping precision
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The timestamping function is extracted from the main computer and implemented as a dedicated hardware component within the input/output module. This extraction eliminates software processing delays and provides direct hardware-level timestamping with precision below one millisecond, while the main computer retains responsibility for signal integrity through its security protocol execution.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The input/output module acts as an intermediary between the main computer and external devices, performing hardware-level timestamping on data before it leaves the system. This intermediary role allows precise timestamping to occur at the fastest possible point in the data path, while the main computer maintains security oversight through protocol validation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If conventional input/output modules are used, then cost is reduced, but timestamping precision and synchronization capability deteriorate

Engineering Contradiction:
ImprovecostVSAvoidtimestamping precision
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent merges a secure clock unit with the input/output module to create an integrated solution that provides both cost-effectiveness and high-precision timestamping. This combination allows the system to use a dedicated hardware clock and timestamping mechanism in the I/O module without requiring the main computer to be significantly more expensive, achieving precision below one millisecond at reasonable cost.

Inventive Principle:
Principle #5Merging (Combining)

4Reliability

If diverse redundancy is implemented in the main computer, then signal safety is achieved, but common mode errors may occur

Engineering Contradiction:
Improvesignal safetyVSAvoidcommon mode errors
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The system is segmented into the main computer and input/output module, with diverse redundancy implemented in the main computer for security-critical functions. The I/O module uses a simplified design that does not require diverse redundancy, as it handles non-critical I/O operations. This segmentation prevents common mode errors from affecting the entire system uniformly, as the I/O module operates independently from the redundant main computer architecture.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3469484B1Data transmission between signal failsafe computing units
Publication Date: 2020.05.27 SIEMENS MOBILITY GMBH
  • EP3469484B1 patent drawingFigure 1
  • EP3469484B1 patent drawingFigure 2
  • EP3469484B1 patent drawingFigure 3~4

AI summary

The invention relates to an input and output module (50) for transmitting and receiving data via a data line (26). The input and output module comprises a protocol machine (118) for a security protocol for data transfer and a clock (16). The protocol machine and instructions for clock processing are stored as sequence control in a read-only memory (17) of the input and output module.