Semiconductor I/O Multiplexer Layout for Multi-Mode DDR Memory
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Solution Overview
Problem
Conventional semiconductor multiplexers face challenges in reducing layout area, particularly in designs requiring multiple operation modes like x4, x8, and x16, leading to increased chip size due to dense driver configurations and layout constraints, especially in DDR2 and DDR3 SDRAMs with 8-bit prefetch architecture.
Innovation Solution
The implementation of first and second multiplexers on either side of global I/O lines, with the first multiplexer between the data I/O pad and global I/O line and the second between the global and local I/O lines, reduces layout area by optimizing driver configurations and spacing, using fewer drivers and input/output multiplexers to manage data transfer efficiently across different operation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple drivers are configured to support x4, x8, and x16 operation modes, then the semiconductor device can operate in multiple data widths, but the layout area increases due to dense driver configurations
Solution Approach 1:
The multiplexer is divided into a first multiplexer and a second multiplexer that operate independently on different segments of the data path. The first multiplexer handles data from I/O pads to global I/O lines, while the second multiplexer handles data from global I/O lines to local I/O lines. This segmentation allows each multiplexer to use fewer drivers (2 drivers per multiplexer instead of 4), reducing layout area while maintaining support for x4, x8, and x16 operation modes through coordinated operation of the two multiplexers.
2Productivity
If drivers are densely configured to handle all operation modes, then data transfer capability is maintained, but internal circuit spacing decreases leading to interference and malfunctions
Solution Approach 1:
By segmenting the multiplexer into two separate multiplexers positioned on either side of the global I/O line, the patent creates sufficient physical spacing between drivers and internal circuits. This segmentation maintains data transfer capability for all operation modes (x4, x8, x16) while preventing circuit interference through improved spatial distribution of components.
Solution Approach 2:
The patent positions the first and second multiplexers on opposite sides of the global I/O line, utilizing the spatial dimension along the signal path rather than concentrating all drivers in a single location. This dimensional arrangement distributes drivers more evenly, maintaining productivity while reducing harmful electromagnetic interference between closely spaced circuits.
Data Source
AI summary
There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.