I/O Pad Circuit Sequencing to Prevent Power-Up Glitches
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Solution Overview
Problem
Conventional I/O circuits face issues with glitches during power ramp-up due to unsuitable signal sequencing controlled by system-level signals, requiring external power-on-control mechanisms that necessitate customer system design modifications, which is inefficient and cumbersome.
Innovation Solution
A gating circuit is introduced to control the signal sequence of data and output enable signals using two separate power-on-control signals, ensuring the data signal is ready before the output enable signal, thereby preventing glitches during power ramp-up without area or performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If system level signals are used to control the signal sequence, then the I/O circuit can operate, but glitches occur during power ramp-up
Solution Approach 1:
The power-on-control mechanism is segmented into two separate signals: a first power-on-control signal for the data signal path and a second power-on-control signal for the output enable signal path. This segmentation allows independent control of signal activation sequences, preventing glitches by ensuring the data signal is ready before the output enable signal activates.
Solution Approach 2:
The first power-on-control signal is activated before the second power-on-control signal, ensuring that the data signal is prepared and stabilized before the output enable signal is activated. This preliminary action prevents the glitch condition where output enable activates before data is ready.
2Reliability
If an external power-on-control mechanism is added to control the I/O circuit in tristate, then glitches are prevented, but customer system design modification is required
Solution Approach 1:
The I/O circuit incorporates an internal power-on-control mechanism that automatically generates and manages the two separate power-on-control signals. This self-service approach eliminates the need for external control mechanisms and removes the burden of system design modification from customers, while still preventing glitches during power ramp-up.
3Device complexity
If the data signal and output enable signal are activated simultaneously, then circuit operation is simplified, but glitches occur during power ramp-up
Solution Approach 1:
The first power-on-control signal activates the data signal path before the second power-on-control signal activates the output enable signal path. This sequential activation ensures that the data signal is fully established and stable before the output enable signal begins driving the I/O pad, preventing glitches while maintaining relatively simple circuit control logic.
Data Source
AI summary
Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.