I/O Path Testing Using Scan Chain Segmentation
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Solution Overview
Problem
Current methods for testing input/output paths in integrated circuits lack sufficient control to accurately determine set-up and hold times and clock-to-out minimum/maximum times, providing only an approximation of the actual timing specifications.
Innovation Solution
The implementation of a circuit arrangement with data path control and clock control circuitry, coupled with multiple flip-flops and scan chains, allows selective coupling of flip-flops to input/output pads and application of clock signals, enabling precise testing of delay times by scanning in data and activating test pulses to measure timing values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test programs are executed on the processor subsystem to write data to and read data from I/O pads, then testing of I/O paths is performed, but sufficient control is not provided to determine set-up and hold times and clock-to-out minimum/maximum times
Solution Approach 1:
The testing system is segmented into two independent scan chains: a first scan chain for controlling data path and clock control flip-flops, and a second scan chain for the receive and transmit flip-flops. This segmentation allows independent configuration and control of each component, enabling precise timing measurements without requiring complex inter-dependent control mechanisms.
Solution Approach 2:
Scan chains are introduced as intermediary structures that provide systematic control and measurement capabilities. The scan chains act as mediators between the test equipment and the flip-flops, enabling precise control of data path configuration and timing measurements without requiring complex direct control logic.
2Measurement precision
If elaborate preparation is performed for testing I/O paths, then testing capability is provided, but only an approximation of actual timing is obtained
Solution Approach 1:
The data path control flip-flops and clock control flip-flops are configured in advance through the first scan chain to establish the desired test conditions, including set-up and hold time configurations and clock-to-out timing parameters. This preliminary configuration enables subsequent precise timing measurements without requiring iterative adjustments during the actual measurement process.
Solution Approach 2:
The scan chain structure enables continuous and systematic control of test conditions. By maintaining configured states in the data path and clock control flip-flops while performing measurements through the second scan chain, the system achieves continuous timing measurements without interruption or reconfiguration, eliminating time loss between measurement cycles.
3Measurement precision
If data path control circuitry and clock control circuitry are added to selectively couple flip-flops to I/O pads and apply clock signals, then precise characterization of I/O path delays is enabled, but device complexity increases
Solution Approach 1:
The data path control circuitry and clock control circuitry are designed with multi-functionality to minimize complexity. The same control structures and scan chain mechanisms used for configuration also serve as measurement pathways, eliminating the need for separate dedicated control and measurement hardware for each timing parameter.
Solution Approach 2:
The control functions for data path configuration and clock signal control are merged into a unified scan chain architecture. Both the data path control flip-flops and clock control flip-flops are integrated into the first scan chain, allowing simultaneous or coordinated control of multiple timing parameters through a single systematic interface, reducing overall circuit complexity.
Data Source
AI summary
Disclosed circuitry includes input-output pads, receive flip-flops, and transmit flip-flops coupled to the input-output pads. Data path control circuitry is coupled to data path control flip-flops, the receive flip-flops and the transmit flip-flops. The data path control circuitry is configured to selectably couple the receive flip-flops and the transmit flip-flops to the input-output pads in response to states of the data path control flip-flops. Clock control circuitry is coupled to clock control flip-flops, the receive flip-flops and the transmit flip-flops. The clock control circuitry is configured to selectably apply one of multiple clock signals to the receive flip-flops and the transmit flip-flops in response to states of the clock control flip-flops. A first scan chain is coupled to the clock control flip-flops and the data path control flip-flops. A second scan chain is coupled to the receive flip-flops and the transmit flip-flops.