I/O Pin Driver Architecture for Low-Interference Voltage Switching
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Solution Overview
Problem
Conventional input/output modules face complexity and interference issues due to frequent switching among different voltages, requiring intricate control operations and multiple combinations of control voltages to set the duty cycle of input/output pins, which complicates the voltage supply circuit and increases interference at the input/output pin.
Innovation Solution
An input/output module with a pre-driver and a post-driver that generates pull-up and pull-down selection signals based on logic levels of an input signal and an enable signal, allowing the post-driver to set the input/output pin to a high-impedance state or change its voltage level accordingly, using a core voltage and supply voltage to simplify control and reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a voltage supply circuit is used to control the voltage of the input/output pin by pull-up or pull-down with multiple combinations of control voltages, then the duty cycle of the input/output pin can be set, but the complexity of the voltage supply circuit increases and interference at the input/output pin increases
Solution Approach 1:
The patent changes the control parameter from multiple voltage levels (2.5V, 4.5V, 0V) to logic levels (0V, 1V) that are already present in the control circuit. This parameter change simplifies the voltage supply circuit while maintaining the ability to control the input/output pin's duty cycle through logical combinations of these two voltage levels.
Solution Approach 2:
The patent extracts the voltage conversion function from the voltage supply circuit by utilizing the existing logic level signals (0V and 1V) from the control circuit. Instead of requiring a complex voltage supply circuit to generate multiple control voltages, the design extracts and reuses the simpler logic signals already available in the system.
2Manufacturing precision
If multiple combinations of control voltages are used to control the input/output pin, then the voltage level can be precisely controlled, but the control operation becomes complicated
Solution Approach 1:
The patent changes the control parameter from multiple voltage levels (2.5V, 4.5V, 0V) to logic levels (0V, 1V) that are already present in the control circuit. This parameter change simplifies the voltage supply circuit while maintaining the ability to control the input/output pin's duty cycle through logical combinations of these two voltage levels.
3Adaptability or versatility
If frequent switching among different voltages is performed to set the duty cycle, then the input/output pin can be controlled, but interference at the input/output pin increases
Solution Approach 1:
The patent changes the control parameter from multiple voltage levels (2.5V, 4.5V, 0V) to logic levels (0V, 1V) that are already present in the control circuit. This parameter change simplifies the voltage supply circuit while maintaining the ability to control the input/output pin's duty cycle through logical combinations of these two voltage levels.
Data Source
AI summary
An input/output module electrically coupled between a control circuit and an input/output pin is provided. The input/output module includes a pre-driver and a post-driver. The pre-driver is electrically coupled to the control circuit, and the post-driver is electrically coupled between the pre-driver and the input/output pin. The pre-driver generates a pull-up selection signal and a pull-down selection signal according to an input signal and an enable signal generated by the control circuit. The post-driver sets a voltage level of the input/output pin according to the pull-up and pull-down selection signals. When the enable signal is at a first logic level, the input/output pin has a high impedance. When the enable signal is at a second logic level, the voltage level of the input/output pin changes with a logic level of the input signal, wherein the first logic level and the second logic level are inverted.


