IO Receiver Transfer-Gate Structure for Low Core Leakage
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Solution Overview
Problem
Conventional IO receivers experience significant core power leakage current when the IO power supply is turned off while the core power supply remains on, due to the inability to detect the power-down state of the IO power supply correctly.
Innovation Solution
The proposed IO receiver design includes a first and second transfer gate with PMOS and NMOS transistors connected in parallel, along with a series connection of inverters powered by separate IO and core power supplies, and additional transistors to manage logic levels, effectively blocking input voltage ranges to minimize leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the IO power supply is turned off while the core power supply remains on, then the IO receiver should be powered down, but core power leakage current occurs due to incorrect detection of the power-down state
Solution Approach 1:
The patent introduces an intermediary detection mechanism that monitors the IO power supply state through the existing signal path. The detection circuit uses the input signal path and internal nodes to sense when the IO power supply is turned off, without requiring direct access to the power supply itself. This intermediary detection resolves the contradiction by enabling reliable power-down state detection while maintaining the separation between core and IO power domains.
Solution Approach 2:
The patent implements a feedback mechanism where the detection circuit continuously monitors the IO power supply state and feeds back control signals to the transfer gates and inverters. When the IO power supply is detected as turned off, the feedback signal triggers the transfer gates to block the input signal path and prevents the inverters from operating, thereby eliminating core power leakage current while ensuring the system responds reliably to the power-down state.
2Loss of energy
If additional transistors and power supply connections are added to detect power-down state, then core power leakage current is reduced, but device complexity increases
Solution Approach 1:
The patent makes the existing transfer gates and inverters multi-functional by enabling them to perform both their normal signal processing function and the additional function of power-down detection and response. The transfer gates serve as both signal transmission paths and power-down detection elements, while the inverters serve as both logic elements and indicators of power supply state. This universality reduces device complexity by reusing existing components for multiple purposes rather than adding dedicated detection circuitry.
Solution Approach 2:
The patent merges the power-down detection function with the existing signal processing path. The detection of IO power supply state is combined with the function of the transfer gates and inverters, so that the same physical structures serve dual purposes: processing input signals and detecting power supply state. This merging eliminates the need for separate detection circuits, thereby reducing overall device complexity while still achieving the goal of reducing core power leakage current.
3Loss of energy
If the transfer gate blocking range is extended to cover the entire input voltage range, then core power leakage current is minimized, but the IO receiver performance is degraded
Solution Approach 1:
The patent makes the transfer gate blocking behavior dynamic by controlling it through the detection circuit that responds to the IO power supply state. When the IO power supply is turned off, the transfer gates dynamically switch to a blocking state that covers the entire input voltage range, minimizing core power leakage current. When the IO power supply is on, the transfer gates dynamically transition to a non-blocking state that allows full signal transmission, maintaining IO receiver performance. This dynamic adaptation resolves the contradiction by making the blocking range conditional rather than fixed.
Solution Approach 2:
The patent implements periodic monitoring of the IO power supply state through the detection circuit, which continuously checks for power-down conditions and periodically adjusts the transfer gate blocking state accordingly. This periodic action ensures that the transfer gates only extend their blocking range when actually needed (during IO power-down scenarios), minimizing core power leakage current at those moments while maintaining normal signal transmission during regular operation, thus preserving IO receiver performance.
Data Source
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AI summary
A receiver (200) includes a first transfer gate (M1, M2), a first inverter (I1), a second inverter (I2), a second transfer gate (MP1, MN1), a third inverter (I3), and a fourth inverter (I4) connected in series, a first power supply supplying power (VDDIO) to the first and second inverters, a second power supply supplying power (VDD) to the third and fourth inverters, a third power supply supplying power (VDDC) to the second transfer gate (MN1, MP1), first and second signals (IEN, IEP) having opposite logic levels for controlling the first transfer gate (M1, M2). The third power supply (VDDC) is significantly lower than the first or second power supply (VDDIO, VDD). The leakage current of the receiver is significantly reduced in the core when the second power supply (VDD) remains on but the first power supply (VDDIO) is turned off while the performance of the receiver remains the same.