I/O Receiver Level Compensation for Full-Swing Drain Voltage
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Solution Overview
Problem
Existing input-output (I/O) receivers in semiconductor integrated circuits face performance degradation due to the inability of the maximum voltage signal at Node B to reach the operational power supply voltage, leading to reduced operation speed.
Innovation Solution
Incorporating a compensation unit comprising PMOS and NMOS transistors to provide a compensation voltage to the drain electrode of the first NMOS transistor, allowing the maximum voltage signal to reach the first power supply voltage, along with a reformation circuit to reshape the voltage signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an NMOS transistor is added to reduce the maximum voltage level at Node B for protection, then the reliability of NMOS transistors is improved, but the operation speed of the I/O receiver deteriorates
Solution Approach 1:
A compensation unit is introduced as an intermediary component between the voltage-level converting unit and ground. This compensation unit includes a compensation NMOS transistor and compensation PMOS transistors that work together to provide compensation current, enabling the maximum voltage signal to reach the operational power supply voltage VDD1 while maintaining protection functionality.
Solution Approach 2:
The invention changes the electrical parameters of the circuit by introducing compensation current through the compensation unit. This compensation current adjusts the voltage levels dynamically, allowing the maximum voltage signal to reach VDD1 (improving speed) while the gate electrode of the first NMOS transistor remains coupled to VDD1 (maintaining protection).
2Reliability
If the gate electrode of the first NMOS transistor is coupled with the power supply voltage VDD1 for protection, then the reliability is improved, but the maximum voltage signal cannot reach VDD1 causing speed degradation
Solution Approach 1:
The protection function is segmented into two independent parts: (1) the gate electrode of the first NMOS transistor coupled to VDD1 for over-voltage protection, and (2) the compensation unit that provides compensation current to enable the maximum voltage signal to reach VDD1. This segmentation allows both protection and high-speed operation to coexist without interference.
Data Source
AI summary
An input-output (I/O) receiver includes a receiving terminal, a first N-type metal-oxide-semiconductor (NMOS) transistor, a reformation circuit, and a compensation unit. The receiving terminal is coupled with an external voltage signal. The first NMOS transistor has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage. The reformation circuit is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. Moreover, the compensation unit is configured to provide a compensation voltage to a voltage signal at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor reaches the first power supply voltage.