Parallel I/O Receiver Phase Adjustors for Link Redundancy Timing
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Solution Overview
Problem
High-speed data communication systems face inefficiencies in power usage due to frequency-dependent losses and stringent timing requirements, particularly in multi-Gb/s data rates, where existing architectures require complex and power-intensive clock synchronization and diagnostics, leading to increased hardware overhead and reduced power efficiency.
Innovation Solution
A parallel input/output interface receiver with two phase adjustors allows for continuous data transmission while calibrating redundant links, using a first phase adjustor for active data and a second for calibration data, enabling phase adjustments during diagnostics without disrupting active data sampling, thus reducing hardware complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single phase adjustor is used for all data receivers, then hardware complexity is reduced, but calibration cannot be performed without interrupting active data transmission
Solution Approach 1:
The phase adjustor functionality is segmented into two separate components: a first phase adjustor for active data channels and a second phase adjustor for calibration channels. This segmentation allows independent operation of calibration and data transmission functions, enabling calibration without interrupting active data transmission while maintaining manageable hardware complexity through modular design.
Solution Approach 2:
The system achieves multi-functionality by having two phase adjustors that can serve different purposes: the first phase adjustor handles active data transmission while the second phase adjustor performs calibration functions. This universal approach allows the system to simultaneously maintain data transmission and perform diagnostics/calibration operations.
2Productivity
If secondary data receivers are added for calibration, then uninterrupted data transmission is enabled, but receiver power and area increase due to doubled complexity
Solution Approach 1:
The calibration function is extracted from the primary data reception function. Instead of adding secondary receivers that duplicate full reception capability, the system extracts only the necessary phase adjustment functionality into a separate second phase adjustor dedicated to calibration operations, reducing the overall receiver complexity while maintaining continuous data transmission capability.
Solution Approach 2:
The system dynamically switches between calibration mode and active data transmission mode by selectively enabling the second phase adjustor during calibration periods while keeping the first phase adjustor active for data transmission. This dynamic operation allows calibration functions to be performed without requiring permanently active secondary receivers, reducing power consumption and hardware complexity.
3Device complexity
If link calibration is performed on active channels, then hardware overhead is reduced, but data transmission is interrupted during calibration
Solution Approach 1:
The system performs preliminary calibration actions on redundant channels before they are needed for active data transmission. By pre-calibrating calibration channels using the second phase adjustor, the system ensures that when calibration is needed, it can be performed without interrupting active data transmission on the first phase adjustor channels, thus avoiding transmission interruptions while maintaining reduced hardware overhead.
4Measurement precision
If more phase adjustment elements are used, then calibration precision is improved, but power consumption increases
Solution Approach 1:
The second phase adjustor is activated periodically only when calibration operations are required, rather than continuously. This periodic action allows the system to maintain high calibration precision when needed while significantly reducing average power consumption, as the additional phase adjustment element is dormant during normal data transmission periods and only becomes active during scheduled calibration intervals.
Data Source
AI summary
Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.