I/O Receiver Voltage Compensation for Full VDD1 Signal Swing
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Solution Overview
Problem
Existing input-output (I/O) receivers in semiconductor integrated circuits cannot fully utilize the operational power supply voltage, leading to reduced operation speed and performance due to the maximum voltage level at Node B being limited to (VDD1-Vthn), which restricts the voltage signal transmission.
Innovation Solution
The proposed I/O receiver includes a receiving terminal, a first NMOS transistor, a reformation circuit, and a compensation unit comprising PMOS and NMOS transistors to provide a compensation voltage, allowing the maximum voltage signal at the drain electrode of the first NMOS transistor to reach the first power supply voltage VDD1, thereby enhancing the voltage signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an NMOS transistor is used to reduce the maximum voltage level at Node B to protect downstream transistors, then the reliability of the circuit is improved, but the operation speed and performance of the I/O receiver deteriorate because the maximum voltage cannot reach the operational power supply voltage
Solution Approach 1:
A compensation unit comprising a PMOS transistor and an NMOS transistor is introduced as an intermediary between the voltage-reducing NMOS transistor and the downstream circuit. This compensation unit actively adjusts the voltage at Node B to reach the operational power supply voltage VDD1, thereby compensating for the voltage reduction and restoring the full voltage swing capability for high-speed operation while maintaining transistor protection through controlled voltage levels.
Solution Approach 2:
The invention dynamically changes the voltage parameter at Node B by introducing a compensation mechanism. The compensation unit modifies the voltage level from the reduced (VDD1-Vthn) to the full operational voltage VDD1, enabling the circuit to operate at maximum speed while the protection mechanism ensures transistor reliability. This parameter transformation resolves the contradiction between protection and performance.
2Reliability
If the maximum voltage level at Node B is limited to (VDD1-Vthn), then the circuit protection is achieved, but the voltage signal transmission capability worsens
Solution Approach 1:
The compensation unit acts as an intermediary that receives the voltage-reduced signal from the protection NMOS transistor and actively restores it to the full operational voltage level. This mediation allows the signal to maintain full transmission capability while the protection mechanism continues to function, effectively decoupling the protection function from the signal transmission quality.
3Reliability
If a voltage reducing NMOS transistor is added to protect the I/O receiver, then the transistor reliability is improved, but the device complexity increases
Solution Approach 1:
The compensation unit merges multiple functions into a single circuit block: voltage compensation, signal buffering, and level restoration. By combining the PMOS and NMOS transistors in a synchronized configuration, the circuit achieves full voltage restoration while maintaining a relatively compact structure that does not excessively increase device complexity.
Solution Approach 2:
The compensation unit performs multiple functions simultaneously: it compensates for voltage reduction, restores the signal to full operational level, provides buffering capability, and maintains compatibility with the existing protection architecture. This multi-functionality justifies the added complexity by delivering comprehensive performance improvement.
Data Source
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AI summary
An input-output "I/O" receiver includes a receiving terminal (PAD), a first N-type metal-oxide-semiconductor "NMOS" transistor (N1), a reformation circuit (202), and a compensation unit (201). The receiving terminal (PAD) is coupled with an external voltage signal. The first NMOS transistor (N1) has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage (VDD1). The reformation circuit (202) is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit (201) includes a first PMOS transistor (P1), a second PMOS transistor (P2), and a second NMOS transistor (N2). Moreover, the compensation unit (201) is configured to provide a compensation voltage to a voltage signal (B) at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor (N1) reaches the first power supply voltage (VDD1).