Reconfigurable I/O Register SERDES for Resource-Efficient Data Conversion
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Solution Overview
Problem
Conventional integrated circuits with hardwired SERDES circuitry are inefficient as they waste resources when SERDES capabilities are not used, and using general-purpose programmable logic resources for SERDES implementation leads to performance limitations and high costs due to routing delays.
Innovation Solution
The input-output circuitry of integrated circuits is configured to selectively form serializer-deserializer circuitry using programmable multiplexer circuitry and data registers, allowing the circuitry to operate in both single-ended and serializer-deserializer modes, enabling flexible and resource-efficient data conversion operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardwired shift registers are used in conventional integrated circuits, then serial-to-parallel and parallel-to-serial data conversion performance is acceptable, but resources are wasted and overhead is increased when SERDES capabilities are not used
Solution Approach 1:
The patent makes the shift register dynamic and reconfigurable by using programmable logic resources instead of hardwired connections. The register can be selectively formed or dissolved based on whether SERDES functionality is needed, allowing the circuit to adapt its structure dynamically. This is achieved through programmable interconnects that can connect logic element registers in series to form shift registers only when required for serial data conversion operations.
Solution Approach 2:
The patent applies universality by using general-purpose programmable logic resources (logic element registers) to perform multiple functions: they can operate as standard logic resources for custom logic design, or be reconfigured to form shift registers for SERDES operations. This multi-functionality eliminates the need for dedicated hardwired shift registers that would sit idle when not needed, thereby improving resource efficiency while maintaining data conversion capability when required.
2Adaptability or versatility
If general purpose programmable logic resources are used to implement serializer-deserializer circuitry, then design flexibility is improved, but performance is limited due to routing delays and implementation costs increase
Solution Approach 1:
The patent applies local quality by using logic element registers that are physically located within the input-output circuit block, close to the serial data interface. This local placement minimizes routing delays compared to using general-purpose programmable logic resources located elsewhere in the device. The interconnects used to form the shift register are localized within the I/O block, reducing the distance signals must travel and thereby maintaining high performance while still providing reconfigurability.
3Adaptability or versatility
If general purpose programmable logic resources are used to implement serializer-deserializer circuitry, then design flexibility is improved, but the amount of programmable circuitry available for custom logic design is reduced
Solution Approach 1:
The patent applies segmentation by dividing the input-output circuit block into distinct functional components: dedicated differential input/output circuitry, and selectively reconfigurable logic element registers. The logic element registers are segmented from the general-purpose programmable logic resources, allowing them to be independently configured for SERDES functionality without consuming the broader programmable logic resources that are needed for custom logic design. This segmentation enables SERDES operations using a dedicated subset of resources while preserving the majority of programmable circuitry for other purposes.
Data Source
AI summary
Input-output circuitry for integrated circuits such as programmable logic device integrated circuits is provided. The input-output circuitry can be configured to operate in a single-ended data mode or a serializer-deserializer mode using programmable routing circuitry such as programmable multiplexers. In single-ended data mode, data registers in the single-ended input-output circuitry may be used to handle transmitted and received single-ended data. In serializer-deserializer mode, the data registers may be configured to form a shift register. The shift register may be used in a serializer-deserializer circuit. Parallel-to-serial and serial-to-parallel data conversion operations may be performed using the shift register. The serializer-deserializer circuit may be connected to differential input-output circuitry such as a differential transmitter circuit or a differential receiver circuit. The data registers may be configured to operate as positive-edge-triggered or negative-edge-triggered devices.