I/O Output Status Detection Circuit Using Edge-Triggered Comparison Windows
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Solution Overview
Problem
Conventional I/O output status detection circuits suffer from incomplete detection due to reliance on external enable signals and limited accuracy caused by threshold voltage configurations, leading to potential missed abnormal states in I/O data bus status.
Innovation Solution
A detection circuit comprising a comparison-window generating circuit and two comparison circuits that generate single pulse signals based on rising and falling edges of I/O data signals, allowing for self-enabled 'interrupt' detection mode without external enable signals, using preset high and low-level reference signals to determine the status of I/O drive signals within defined time windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional hysteresis comparison circuit with threshold voltage is used for detection, then the detection circuit can operate with a simple structure, but the detection accuracy is insufficient due to threshold voltage being affected by circuit configuration
Solution Approach 1:
The detection circuit is segmented into multiple independent comparison circuits, each responsible for detecting specific abnormal states (over-voltage, under-voltage, over-current, under-current). This segmentation allows each circuit to use simple threshold comparison while collectively achieving comprehensive and accurate detection of all abnormal states without requiring a complex unified circuit configuration.
2Reliability
If an external enable signal controls the detection operation, then the circuit can operate in a controlled manner, but abnormal states may be missed when the enable signal is invalid
Solution Approach 1:
The detection circuit performs self-service by automatically activating itself through internal enable signals generated from the detection of data signal edges. When the comparison circuit detects a rising or falling edge of the data signal, it automatically generates an internal enable signal to activate the relevant comparison operation, eliminating dependency on external enable signals and ensuring continuous monitoring of abnormal states.
3Measurement precision
If a single comparison circuit with fixed threshold is used, then the circuit structure is simple, but it cannot accurately detect both high-level and low-level abnormal states
Solution Approach 1:
The detection system uses asymmetric design by implementing separate comparison circuits with different threshold values for detecting high-level abnormalities (over-voltage, over-current) and low-level abnormalities (under-voltage, under-current). Each circuit is optimized with appropriate threshold settings for its specific detection task, enabling accurate detection of both high and low abnormal states while maintaining relatively simple individual circuit structures.
Data Source
AI summary
A detection circuit, a detection method, and an electronic system for detecting an I/O output status are provided. The detection circuit includes a comparison-window generating circuit configured to: detect an I/O data signal, generate a first single pulse signal, determining a first-time window, in response to a rising edge of the I/O data signal, and generate a second single pulse signal, determining a second-time window, in response to a falling edge of the I/O data signal. A first comparison circuit is configured to: receive the first single pulse signal, and compare the I/O drive signal with a preset high-level reference signal within the first time window to obtain a first comparison result. The second comparison circuit is configured to: receive the second single pulse signal, and compare the I/O drive signal with a preset low-level reference signal within the second time window to obtain a second comparison result.