I/O Synchronization Engine for High Integrity Multicore Processing
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Solution Overview
Problem
Modern processor architectures, particularly in System on a Chip (SoC) designs, pose challenges in achieving high-integrity computing due to asynchronous hardware events and performance-driven designs that are not deterministic, making granular lock-stepping difficult without custom hardware or software, especially when using commercial off-the-shelf devices.
Innovation Solution
A system for input/output synchronization in a multi-core processing environment that includes logical processing units with multiple homogeneous cores running the same guest operating system, an I/O synchronization engine for verifying and replicating output data, and a hypervisor for synchronizing data receipt, allowing for high-integrity operation on a single silicon device without requiring multiple physical computation channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If granular lockstepping is implemented using classical architectural approach with two discrete host processors, then high integrity computing is achieved, but device complexity and hardware requirements increase significantly
Solution Approach 1:
The patent merges multiple processing cores onto a single silicon device (System on Chip), integrating what were previously separate discrete processors into one unified hardware platform. This consolidation maintains the redundancy needed for high-integrity computing while reducing overall device complexity and hardware requirements.
Solution Approach 2:
The patent creates a universal processing platform that can execute multiple guest operating systems concurrently on different cores within a single device. This multi-functional approach allows the same hardware to provide both computational redundancy and general-purpose processing capabilities, eliminating the need for specialized dual-processor configurations.
2Productivity
If performance-driven architectures with asynchronous hardware events are adopted in modern SoC designs, then processing speed and efficiency improve, but synchronization difficulty and determinism decrease
Solution Approach 1:
The patent segments the synchronization problem into manageable parts by introducing virtualization layers and isolated execution environments for each guest operating system. This allows asynchronous hardware events to be handled independently within each virtualized context while maintaining overall system coherence, reducing the complexity of global synchronization.
Solution Approach 2:
The patent introduces intermediary software layers (virtual machine monitors, hypervisors) that mediate between the asynchronous hardware events and the guest operating systems. These intermediaries provide deterministic interfaces and abstraction layers that hide the complexity of asynchronous event handling from the application logic.
3Reliability
If custom hardware or software is used to achieve high-integrity operation on COTS devices, then reliability is improved, but ease of manufacture and cost increase
Solution Approach 1:
The patent makes commercial off-the-shelf multi-core processors universally suitable for high-integrity applications by implementing software-based virtualization and synchronization mechanisms. This approach eliminates the need for custom hardware modifications or specialized processors, allowing standard COTS devices to provide certified high-integrity operation through software configurations and methodologies.
Data Source
AI summary
A system and related method for I/O synchronization in a high integrity multi-core processing environment (MCPE) incorporates logical computing units (LCU) of two or more homogeneous processing cores, each core running a guest operating system (GOS) and user applications such that the homogeneous cores concurrently generate the same output data (which the GOS loads to an I/O synchronization engine (IOSE)) or receive the same output data from the IOSE. The IOSE verifies data integrity by comparing the concurrently received datasets and selects a verified dataset for routing to other cores or externally to the MCPE. The IOSE receives and atomically replicates input data for synchronous transfer to, and consumption by, the user applications running on the cores of the LCU.