I/O Transistor Deeper Source/Drain Regions for Leak Current Suppression
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Solution Overview
Problem
In semiconductor devices, the segregation of boron impurities at the interface between the silicon substrate and the oxide film leads to a shorter drain region, increasing the likelihood of leak current between the silicide region and the support substrate, particularly in n-type MOSFETs, which existing technologies fail to effectively suppress.
Innovation Solution
The semiconductor device incorporates n-channel and p-channel transistors with deeper impurity regions for I/O circuits compared to logic circuits, ensuring a longer distance between the drain region and the depletion layer, even when segregation occurs, thereby reducing the likelihood of leak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a deep source/drain region is formed in the I/O transistor to increase the distance between the silicide region and depletion layer, then leak current is suppressed, but the structure complexity increases due to different depths for core and I/O transistors
Solution Approach 1:
The invention divides the semiconductor device into two distinct regions: a first region containing core transistors with a first source/drain region depth, and a second region containing I/O transistors with a second source/drain region depth. This segmentation allows each region to be optimized independently, with the I/O region having a deeper source/drain region to suppress leak current while the core region maintains its original design, thus resolving the contradiction between reliability improvement and device complexity.
2Productivity
If boron impurity concentration is increased in the substrate to improve transistor performance, then segregation at the oxide film interface occurs, shortening the drain region and increasing leak current
Solution Approach 1:
The invention extracts the problematic boron impurity from the I/O transistor region by forming a boron-free or low-boron impurity region in the substrate underlying the I/O transistor's source/drain region. This extraction prevents segregation at the oxide film interface, maintains the drain region length, and suppresses leak current while allowing high-performance transistors to be formed in the core region with normal boron doping.
3Reliability
If high voltage is applied to the I/O transistor during burn-in to test reliability, then leak current between silicide region and substrate increases due to depletion layer contact with silicide
Solution Approach 1:
The invention performs a preliminary action by forming a deep source/drain region in the I/O transistor before the burn-in test. This deep source/drain region creates a longer distance between the silicide region and the depletion layer, so when high voltage is applied during burn-in testing, the depletion layer does not contact the silicide region, thereby preventing leak current generation and allowing reliable burn-in testing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses leak current generation at the drain region, enhancing the reliability of semiconductor devices by maintaining a deeper impurity region in n-type MOSFETs and reducing the impact of segregation, especially under high voltage conditions.
Implementation Method 1
the segregation of boron impurities at the interface between the silicon substrate and the oxide film
Implementation Method 2
a depletion layer is likely to come into contact with the silicide region of the drain region due to a large voltage applied to the drain region
Data Source
AI summary
A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.