I/O Transistor Gate Dielectric Stack for Breakdown Voltage Control
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Solution Overview
Problem
High integration density semiconductor integrated circuits face challenges in scaling transistors for input/output (I/O) operations while maintaining compatibility with logic and memory transistors, requiring independent control of breakdown voltage and leakage without affecting carrier mobility and bias temperature instability (BTI) parameters.
Innovation Solution
A gate dielectric stack comprising an oxynitride layer and a composite layer of interlayer and high-k (Hi-K) material is used, allowing for independent control of breakdown voltage and inversion layer scaling, with processes common to both logic and I/O transistors, including forming an oxynitride layer, depositing Hi-K material, and forming an interlayer dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If I/O transistors are designed with increased size and breakdown voltage to interface with external circuits, then voltage and current handling capability is improved, but leakage and carrier mobility are adversely affected
Solution Approach 1:
The gate dielectric is segmented into multiple layers: a first gate dielectric layer with high breakdown voltage characteristics and a second gate dielectric layer with low leakage characteristics. This segmentation allows each layer to independently optimize for its specific function, resolving the contradiction between high breakdown voltage and low leakage in I/O transistors.
Solution Approach 2:
The gate dielectric structure uses composite materials with different electrical properties stacked together. The first layer (e.g., silicon oxide) provides high breakdown voltage, while the second layer (e.g., silicon nitride or oxynitride) provides low leakage and protects the inversion layer, creating a composite structure that simultaneously achieves both requirements.
2Productivity
If transistors are scaled to minimum feature dimensions for high integration density, then integration density and signal propagation speed are improved, but voltage handling capability and noise immunity deteriorate
Solution Approach 1:
Different regions of the semiconductor device are given different gate dielectric structures: logic transistors use a first gate dielectric structure optimized for high-density scaling, while I/O transistors use a second gate dielectric structure with enhanced breakdown voltage and noise immunity. This local differentiation allows each region to optimize for its specific functional requirements.
Solution Approach 2:
The gate dielectric parameters (material composition, thickness, dielectric constant) are changed between logic and I/O transistor regions. I/O transistors use a composite gate dielectric with adjusted thickness ratios and material properties to achieve higher breakdown voltage and noise immunity while logic transistors maintain optimized parameters for high-density operation.
3Loss of energy
If logic transistors operate at reduced voltages for high-density operation, then heat generation and power consumption are reduced, but interface capability with external circuits deteriorates
Solution Approach 1:
The semiconductor device is segmented into logic regions operating at low voltage for energy efficiency and I/O regions operating at higher voltage for external interface capability. The separate gate dielectric structures enable this voltage segmentation without requiring different process technologies.
Solution Approach 2:
The gate dielectric formation processes are designed to be universal and common to both logic and I/O transistor fabrication. The same deposition and processing equipment can form both gate dielectric structures, allowing the system to achieve multi-functionality (low-power logic operation and high-voltage I/O interfacing) through a unified manufacturing process.
Data Source
AI summary
A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.