Multi-Mode I/O Transmitter Serializer With Low-Latency Equalization
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Solution Overview
Problem
Existing multi-modes serialization technologies face challenges in achieving timing closure due to separate timing paths, incur additional pad capacitance, and introduce 1-cycle latency through pipe-stage delays, while also lacking efficient control over drive strength and equalization.
Innovation Solution
A configurable I/O transmitter circuitry using multiple FIFO buffers, flip-flops, and multiplexers to support 4:1 and 2:1 serializer modes with equalization features, including de-emphasis and pre-emphasis, and a bypass path for low pad capacitance and asynchronous transfers, utilizing a 0-degree and 90-degree shifted clock for data sampling and outputting, and an output enable signal for drive strength control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple dedicated serializers are instantiated and multiplexed at the output to support multiple modes serialization, then multi-mode serialization capability is achieved, but timing closure becomes harder to achieve due to separate timing paths
Solution Approach 1:
The patent merges multiple serialization modes into a single unified serializer circuit by using a multi-phase clock generator that provides different clock phases (e.g., 0-degree, 90-degree shifted clocks) to the same serializer. This allows the single serializer to operate in different modes (such as 4:1 or 2:1 serialization) by switching between clock phases, thereby achieving multi-mode capability without creating separate timing paths for each mode.
Solution Approach 2:
The serializer is designed with universal functionality to handle multiple serialization modes through a single circuit instance. The same serializer circuit can be configured for different serialization ratios (e.g., 4:1, 2:1) by selecting different clock phases from the multi-phase clock generator, making the circuit multi-functional and eliminating the need for dedicated serializers for each mode.
2Reliability
If separate drivers are used for de-emphasis and pre-emphasis equalization along the main driver, then equalization control is achieved, but additional pad capacitance is incurred which degrades the overall performance and timing of the transmit path
Solution Approach 1:
The patent combines the main driver and equalization drivers into a single integrated driver circuit. The driver circuit is designed to perform both de-emphasis and pre-emphasis equalization functions along with the main driving function, thereby eliminating the need for separate dedicated drivers. This integration reduces the total number of drivers and consequently reduces the overall pad capacitance while maintaining full equalization capability.
3Reliability
If pipe-stage delay is added to obtain future data for transmit equalizer architectures, then equalization control is achieved, but 1 cycle latency is introduced which delays the output
Solution Approach 1:
The patent implements preliminary action by using a multi-phase clock generator that pre-generates multiple clock phases (including future phases) without requiring pipe-stage delays. The serializer can access future data by synchronizing with appropriate clock phases that are already available, thereby obtaining the information needed for equalization control without introducing the 1-cycle latency that would result from adding delay stages to the data path.
Data Source
AI summary
A I/O transmitter circuitry for supporting multi-modes serialization comprising a serializer, wherein said serializer comprising a multiple FIFO buffers, a multiple flip-flops including a first latch, a second latch, a third flop and a fourth flop, to hold data ready and stage the data for subsequent muxing, a 0-degree shifted clock and a 90-degree shifted clock and a multiplexer, wherein a read pointer reads one bit of data from each of the FIFO buffers, wherein the data is sampled into the respective flip-flops according to frequency of the 0-degree shifted clock and 90-degree shifted clock, wherein the data is outputted by the 0-degree shifted clock and 90-degree shifted clock via the multiplexer.