On-Chip I/O Testing Circuit for Characterization
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Solution Overview
Problem
Current on-chip testing methods for I/O structures are time-intensive, prone to instrument errors, and costly, as they require manual testing and sophisticated equipment, failing to adequately characterize I/O pin parameters across various technologies and process spreads.
Innovation Solution
A flexible on-chip testing circuit with a programmable test program and central processing controller, utilizing operational modes for measuring I/O characterization, including DC and AC parameters, through a standard test interface and characterization modules, enabling automated and cost-effective testing across multiple I/O structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual testing methods are used for I/O characterization, then comprehensive measurement of DC and AC parameters can be achieved, but test time becomes extremely long and prone to instrument errors
Solution Approach 1:
The patent implements self-service by embedding a test controller and state machine directly on the chip that automatically executes test sequences, applies test patterns, and measures I/O parameters without requiring manual external testing. The on-chip controller autonomously manages the entire characterization process, reducing both test time and instrument errors while maintaining comprehensive measurement capabilities.
Solution Approach 2:
The patent replaces manual mechanical testing operations with automated electronic control systems. The embedded state machine and controller electronically generate test patterns, automatically switch between DC and AC measurement modes, and digitally process measurement results, eliminating the need for manual instrument operation and significantly reducing test duration.
2Measurement precision
If sophisticated external testers are used for I/O characterization, then comprehensive parameter measurement is possible, but testing cost increases enormously
Solution Approach 1:
The patent merges the testing functionality directly into the chip by integrating a test controller, state machine, and measurement circuits on the same substrate. This consolidation eliminates the need for expensive external sophisticated testers, as the chip itself performs its own characterization, thereby dramatically reducing testing costs while maintaining comprehensive measurement capabilities.
Solution Approach 2:
The embedded test controller is designed to perform multiple functions including DC parameter measurement, AC parameter measurement, and automated test sequence execution. This multi-functional on-chip testing system replaces the need for multiple specialized external instruments, reducing overall testing cost while maintaining comprehensive characterization capabilities.
3Productivity
If automated wafer-level testing is implemented, then test time is reduced, but device complexity increases due to embedded test features
Solution Approach 1:
The patent segments the testing system into modular components: a test controller unit, a state machine unit, and measurement units for DC and AC parameters. This segmentation allows the complex automated testing functionality to be organized into manageable modules that can be systematically integrated on-chip, reducing the perceived complexity while enabling high-speed automated wafer-level testing.
Data Source
AI summary
The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.