IOMMU Address Translation Table Synchronization via Processor Messages
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Solution Overview
Problem
Conventional address translation table mechanisms are inefficient due to limited IOMMU access, leading to increased processing time and potential system faults, as the IOMMU can only read from the table and lacks the ability to store additional performance-tracking information, and the update process is cumbersome, requiring the IOMMU to walk the table to delete and recreate cache entries.
Innovation Solution
The processor sends a message to the IOMMU with the updated physical memory location and a new pointer, allowing the IOMMU to update both the address translation table and cache entries, enabling write access and bypassing old branches, thus improving efficiency and reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the IOMMU is restricted to read-only access of the address translation table, then the processor can maintain table coherence and avoid conflicts, but the IOMMU cannot store additional performance-tracking information or update entries efficiently
Solution Approach 1:
The patent divides the address translation table into two separate structures: a read-only table maintained by the processor for coherence, and a read-write translation buffer maintained by the IOMMU for performance tracking. This segmentation allows each component to operate independently with appropriate access rights, resolving the contradiction between versatility and reliability.
Solution Approach 2:
The patent introduces a translation buffer as an intermediary structure between the processor and the address translation table. This buffer receives updates from the processor and provides read-write access to the IOMMU, enabling the IOMMU to store additional information without compromising system coherence.
2Loss of time
If the processor maintains the address translation table exclusively, then coherence is maintained, but the IOMMU must walk the tree to update cache entries, increasing processing time
Solution Approach 1:
The processor prepares the new translation table entry with the updated physical address before sending the update to the IOMMU. This preliminary preparation eliminates the need for the IOMMU to walk the tree structure during updates, as the IOMMU receives ready-to-use entry data directly from the processor.
Solution Approach 2:
The patent creates a copy of the translation table entry in the translation buffer that the IOMMU can read and write to. This copy mechanism allows the IOMMU to update cache entries efficiently without accessing the original table structure, reducing processing time.
3Loss of time
If the IOMMU walks the address translation table to delete and recreate cache entries, then coherence is maintained, but processing time increases significantly
Solution Approach 1:
The patent extracts the cache entry deletion operation from the tree-walking process. The IOMMU receives a direct indication of which cache entry needs to be deleted and performs the deletion locally without walking the entire tree structure, significantly reducing processing time while maintaining coherence.
Solution Approach 2:
The processor sends feedback information to the IOMMU about cache entry status and physical address changes. This feedback mechanism allows the IOMMU to update cache entries directly based on received information rather than walking the table, reducing processing time while maintaining reliability.
Data Source
AI summary
A system, method and computer-readable medium for updating an address translation table. In the method, a message indicating a physical memory location that corresponds to a virtual address is received from a processor. An I/O Memory Management Unit (IOMMU) is used to update an entry within the address translation table corresponding to the virtual address according to the indicated physical memory location.