Host IOMMU Translation Bypass for Virtual Machine Efficiency
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Solution Overview
Problem
The overhead associated with guest bus address translation by the hypervisor in virtualization systems, particularly in network function virtualization, leads to computing inefficiency and reduced processing resources, as it involves significant translation overhead for a large number of small access requests.
Innovation Solution
Implementing a method for hypervisor translation bypass by reserving a physical bus address range, allowing the host input-output memory management unit to handle device access requests, thereby reducing the need for hypervisor translation and freeing up processing resources for more requests, enabling more guest virtual machines to run without performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the hypervisor handles guest bus address translation for device access requests, then address translation is performed correctly, but processing overhead increases and computing efficiency decreases
Solution Approach 1:
The patent extracts the address translation function from the hypervisor and assigns it to the host IOMMU. The host IOMMU is configured with a physical bus address range that includes the allowed address range, enabling it to handle translation requests directly without hypervisor intervention. This extraction reduces the hypervisor's processing overhead while maintaining translation correctness through the host IOMMU's hardware-based translation capability.
Solution Approach 2:
The patent introduces the host IOMMU as an intermediary between the guest virtual machine and the physical memory. The host IOMMU receives device access requests, performs address translation using the configured physical bus address range, and accesses physical memory directly. This intermediary mechanism eliminates the need for hypervisor-mediated translation, improving processing efficiency while ensuring correct address mapping.
2Ease of operation
If the hypervisor processes a large number of small access requests, then all requests are handled, but processing resources are consumed and performance degrades
Solution Approach 1:
The patent enables the host IOMMU to self-serve by configuring it with the physical bus address range. The host IOMMU autonomously handles address translation and device access requests without requiring hypervisor intervention for each request. This self-service mechanism significantly reduces processing resource consumption while maintaining full request handling capability, as the host IOMMU processes requests independently at hardware speed.
3Productivity
If more guest virtual machines are run on one physical server, then hardware utilization improves, but translation overhead increases
Solution Approach 1:
The patent extracts the translation overhead from the hypervisor and assigns it to the host IOMMU. By configuring the host IOMMU with the physical bus address range, each guest virtual machine's address translation requests are handled directly by the host IOMMU without hypervisor intervention. This extraction eliminates the cumulative translation overhead that would otherwise increase with more virtual machines, allowing higher hardware utilization without proportional increases in translation time.
Data Source
AI summary
A system and method of translation bypass includes a hypervisor retrieving a physical bus address range from a host input-output memory management unit. The hypervisor reserves an allowed address range of the physical bus address range, and sends the allowed address range to a guest virtual machine. Sending the allowed address range sets a guest bus address range mapped by a virtual input-output memory management unit. The guest virtual machine is prevented from accessing any bus address outside of the allowed address range. The hypervisor receives, from the guest virtual machine, an access request to a guest bus address, which is an address within the allowed address range. The hypervisor stores the access request to the guest bus address in physical memory mapped in the host input-output memory management unit to an address outside of the allowed address range.