IOMMU DMA Address Translation for Virtual Machine Security

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Solution Overview

Problem

In computer systems, especially virtual machine environments, input/output (I/O) devices use physical addresses, which reduces system security and complicates memory management, as rogue devices can access memory unimpeded, impacting performance due to unoptimized direct memory access (DMA) transfers.

Innovation Solution

An Input/Output Memory Management Unit (IOMMU) is introduced, which includes memory for storing translation data and control logic to translate I/O device-generated memory requests using device table entries and I/O page tables, ensuring secure and optimized DMA operations by converting virtual addresses to physical addresses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If I/O devices use physical addresses to access memory, then device access simplicity is improved, but system security deteriorates

Engineering Contradiction:
Improvedevice access simplicityVSAvoidsystem security
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces an I/O Memory Management Unit (IOMMU) as an intermediary component between I/O devices and system memory. The IOMMU translates I/O device-generated virtual addresses to physical addresses, preventing rogue devices from directly accessing memory using physical addresses. This mediator maintains security while allowing I/O devices to operate with simplified virtual addressing, similar to how CPU memory management works.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If I/O devices use physical addresses, then direct memory access speed is improved, but memory management complexity deteriorates

Engineering Contradiction:
Improvedirect memory access speedVSAvoidmemory management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments memory management functionality into separate components: the IOMMU handles I/O device address translation independently from the CPU memory management unit. This segmentation allows I/O devices to use virtual addresses while maintaining fast DMA transfers, as the IOMMU is specifically optimized for I/O address translation without interfering with CPU memory management operations.

Inventive Principle:
Principle #1Segmentation

3Reliability

If translation is implemented for I/O devices, then system security is improved, but address translation overhead increases

Engineering Contradiction:
Improvesystem securityVSAvoidaddress translation overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by pre-configuring the IOMMU with translation tables and device-specific translation parameters before I/O operations begin. The IOMMU caches translation mappings and maintains translation state information, allowing rapid address translation during DMA operations without repeated table lookups. This preliminary setup minimizes translation overhead while maintaining security benefits.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7809923B2Direct memory access (DMA) address translation in an input/output memory management unit (IOMMU)
Publication Date: 2010.10.05 MEDIATEK INC
  • US7809923B2 patent drawing
  • US7809923B2 patent drawing
  • US7809923B2 patent drawing

AI summary

In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translation data. The translation data corresponds to one or more device table entries in a device table stored in a memory system of a computer system that includes the IOMMU, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device that generates the request. The translation data further corresponds to one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request.