IOMMU Host Permission Table for Secure Address Translation

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Solution Overview

Problem

Current Address Translation Services (ATS) in PCIe systems perform limited security checks, making them vulnerable to malicious devices that can perform unauthorized memory operations, compromising security and requiring a trade-off between performance and security.

Innovation Solution

Implementing a Host Permission Table (HPT) managed by the IOMMU to enforce access control, ensuring that devices can only access memory addresses explicitly assigned to them, with page access permissions verified before allowing memory operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If limited security checks are performed in current ATS, then performance is maintained, but security is compromised allowing unauthorized memory access

Engineering Contradiction:
ImprovesecurityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by establishing access permission rules in advance through the Host Permission Table (HPT) before memory access operations occur. The HPT pre-defines which devices can access specific memory addresses, so when a memory access request is made, the translation agent can quickly verify permissions without performing complex security checks during the actual access, thus maintaining both security and performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism - the Host Permission Table (HPT) managed by the translation agent (IOMMU) - that mediates between devices and memory resources. This intermediary enforces access control by translating device addresses and checking permissions against the HPT, preventing direct unauthorized access while maintaining efficient memory operations for authorized devices

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If strict access control is enforced to prevent unauthorized access, then security is improved, but device complexity and overhead increase

Engineering Contradiction:
ImprovesecurityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The translation agent performs self-service by autonomously managing the Host Permission Table and automatically enforcing access control decisions. The IOMMU independently verifies device permissions against the HPT without requiring intervention from the host processor or additional security management hardware, reducing system complexity while maintaining strict access control

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The translation agent serves multiple functions: it performs address translation from device addresses to host physical addresses, manages the Host Permission Table, and enforces access control all in one component. This multi-functionality eliminates the need for separate security management hardware or complex software routines, reducing overall system complexity while providing comprehensive security

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11921646B2Secure address translation services using a permission table
Publication Date: 2024.03.05 INTEL CORP
  • US11921646B2 patent drawing
  • US11921646B2 patent drawing
  • US11921646B2 patent drawing

AI summary

Embodiments are directed to providing a secure address translation service. An embodiment of a system includes memory for storage of data, an IOMMU coupled to the memory, and a host-to-device link to couple the IOMMU with one or more devices and to operate as a translation agent on behalf of one or more devices in connection with memory operations relating to the memory, including receiving a translated request from a discrete device via the host-to-device link specifying a memory operation and a physical address within the memory pertaining to the memory operation, determining page access permissions assigned to a context of the discrete device for a physical page of the memory within which the physical address resides, allowing the memory operation to proceed when the page access permissions permit the memory operation, and blocking the memory operation when the page access permissions do not permit the memory operation.