Processor Interrupt Routing via IOMMU for Performance State Adjustment
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Solution Overview
Problem
In computer systems, handling device interrupts is inefficient due to the inability to timely adjust the performance state of processing engines, as the destination processing engine for interrupt handling is unknown until after the initial handler has completed processing.
Innovation Solution
A processor with a memory management unit that routes interrupts directly to a specified destination in user space, allowing the power management unit to adjust the performance state for handling the interrupt, thereby improving interrupt handling performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the destination processing engine is determined after the initial handler completes processing, then the interrupt routing follows a conventional sequential approach, but the performance state adjustment cannot be made timely enough to improve interrupt handling efficiency
Solution Approach 1:
The patent applies preliminary action by pre-determining the destination processing engine for interrupt handling before the initial handler completes its processing. The memory management unit is configured to route interrupts directly to the specified destination, allowing the power management unit to adjust the performance state in advance. This eliminates the time delay associated with waiting for the initial handler to complete before routing the interrupt and adjusting performance states.
2Use of energy by moving object
If the performance state is adjusted after interrupt routing is determined, then the system maintains simplicity in interrupt management, but the ability to optimize power consumption and performance is limited
Solution Approach 1:
The patent merges the functions of interrupt routing and performance state management by integrating the destination determination into the memory management unit's interrupt routing logic. The power management unit receives notification of the destined processing engine and coordinates performance state adjustments seamlessly. This unified approach enables power consumption optimization without significantly increasing overall system complexity.
3Adaptability or versatility
If the interrupt destination is unknown until after initial processing, then the interrupt handling follows a traditional sequential model, but opportunities for performance optimization and energy efficiency are lost
Solution Approach 1:
The patent introduces an intermediary mechanism where the memory management unit acts as a mediator between the initial interrupt handler and the destination processing engine. The MMU is configured with information about the destined processing engine and uses this to directly route interrupts, enabling the power management unit to adapt performance states appropriately. This intermediary approach enhances performance state adaptability while maintaining relatively simple interrupt routing logic.
Data Source
AI summary
In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.