IOMMU Memory Fence for PCIe DMA Violation Detection

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Solution Overview

Problem

Developing device drivers for devices with a DMA engine is challenging due to the difficulty in detecting unintentional or intentional memory space accesses outside the specified area, leading to functional errors or security breaches, which are hard to debug and can result in system failures or malicious activities.

Innovation Solution

Enabling the I/O Memory Management Unit (IOMMU) to re-map physical memory addresses to virtual addresses, allocating a memory fence area, adding a PCIe device, and monitoring DMA accesses to detect memory space violations, thereby flagging errors and preventing unauthorized access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If DMA engine is used for memory access, then data transfer speed is improved, but memory address violation detection becomes difficult

Engineering Contradiction:

Improvedata transfer speedVSAvoidmemory address violation detection

Core Design Contradiction:

SpeedVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces an intermediary mechanism (IOMMU with memory fence area) between the DMA engine and memory space. This intermediary monitors and controls memory accesses, detecting violations without slowing down the DMA data transfer operation. The IOMMU acts as a mediator that allows high-speed DMA while providing detection capability through the memory fence area configuration.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary action by configuring the memory fence area before DMA operations occur. By pre-establishing the permitted memory address range through IOMMU configuration, the system is prepared to detect any attempted violations. This preliminary setup enables detection without interfering with the actual high-speed data transfer process.

Inventive Principle:

Principle #10Preliminary action

2Difficulty of detecting and measuring

If memory access monitoring is added, then detection capability is improved, but system complexity increases

Engineering Contradiction:

Improvememory access detection capabilityVSAvoidsystem complexity

Core Design Contradiction:

Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent makes the IOMMU multi-functional by using it for both memory management and security monitoring purposes. Rather than adding a separate dedicated monitoring system, the existing IOMMU is extended to provide both address translation and violation detection functions. This universality reduces overall system complexity while improving detection capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the memory management function and security monitoring function into a single IOMMU component. By combining these functions, the system avoids the complexity of having separate monitoring hardware or software layers. The memory fence area is integrated within the IOMMU structure, allowing both translation and detection to occur in one unified component.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11853179B1Detection of a DMA (direct memory access) memory address violation when testing PCIE devices

Publication Date: 2023.12.26 TELEDYNE LECROY INC

AI summary

A method for detecting a Direct Memory Access (DMA) memory address violation when testing PCIe devices is disclosed. The method for detecting a DMA memory address violation when testing PCIe devices applies to unintentional and intentional accesses of memory space outside of an area in memory specified by the device driver developed for the device.