IOMMU Address Translation Request Reordering for Resource Fairness
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Solution Overview
Problem
In highly integrated System on Chip (SoC) environments, independent address translation requests from I/O devices can lead to resource competition and denial-of-service attacks, as one high-bandwidth device can starve others of address translation services, necessitating a more efficient allocation of IOMMU resources.
Innovation Solution
The IOMMU reorders and allocates address translation requests based on policies associated with each I/O device, using quality-of-service policies and hardware resources, such as level one translation lookaside buffers and page table walkers, to ensure fair distribution and prevent resource overloading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the IOMMU services address translation requests from multiple I/O devices without prioritization, then all devices can access memory, but high-bandwidth devices can starve other devices of address translation services
Solution Approach 1:
The patent segments the IOMMU's address translation resources into multiple priority queues (high priority and low priority). This segmentation allows the system to differentiate between critical and non-critical address translation requests, ensuring that high-priority devices receive timely service while preventing any single device from monopolizing all resources. The segmented queue structure directly resolves the contradiction by maintaining both high throughput for bandwidth-intensive devices and reliable service availability for all devices.
Solution Approach 2:
The patent applies local quality by assigning different service qualities to different I/O devices based on their priority levels. High-priority devices receive preferential treatment with dedicated high-priority queue access and guaranteed service, while low-priority devices receive standard service. This localized quality differentiation ensures that critical devices maintain reliable service availability while the overall system achieves high productivity through efficient resource allocation to bandwidth-intensive operations.
2Productivity
If the IOMMU processes all address translation requests in a shared queue, then resource utilization is maximized, but malicious software can mount denial-of-service attacks by flooding the IOMMU
Solution Approach 1:
The patent implements preliminary action by establishing priority queues and service policies before address translation requests are processed. The system pre-configures high-priority and low-priority queues, assigns devices to appropriate priority levels, and sets up service guarantees in advance. This preliminary structuring prevents denial-of-service attacks by ensuring that even if malicious software generates excessive requests, the IOMMU can prioritize legitimate high-priority requests and maintain service availability, while still utilizing resources efficiently through the pre-established queue structure.
3Productivity
If the IOMMU allocates hardware resources dynamically based on device needs, then performance is optimized, but resource allocation complexity increases
Solution Approach 1:
The patent applies dynamics by implementing a flexible priority-based resource allocation mechanism that can adapt to different device needs. The system dynamically assigns address translation requests to high-priority or low-priority queues based on device attributes and current system conditions. This dynamic allocation optimizes performance by directing resources to bandwidth-intensive operations when needed while maintaining simplicity through clear priority-based rules, avoiding the need for complex allocation algorithms.
Data Source
AI summary
A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.