IOMMU Reverse Map Table for VM Memory Access Control
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Solution Overview
Problem
Hypervisors in computing devices may fail to properly enforce access controls, leading to potential data breaches by allowing virtual machines to access incorrect or unauthorized memory areas, due to incorrect address translations provided by the hypervisor.
Innovation Solution
A reverse map table is implemented to ensure that system physical addresses are properly mapped to guest physical addresses, with checks performed by the IO table walker to verify the validity of these mappings and prevent unauthorized access, and a modified Address Translation Caching (ATC) scheme is used to provide only partial address translation information to IO devices, ensuring that only valid translations are used for memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the hypervisor provides address translations to enable IO devices to access memory pages allocated to virtual machines, then memory access functionality is improved, but security deteriorates because the hypervisor may provide incorrect address information allowing unauthorized access
Solution Approach 1:
An Input-Output Memory Management Unit (IOMMU) is introduced as an intermediary component between IO devices and memory. The IOMMU performs address translation for IO devices independently of the hypervisor, using its own address translation tables. This mediator prevents the hypervisor from directly controlling IO device memory access, thereby maintaining security even if the hypervisor provides incorrect address information.
Solution Approach 2:
The address translation functionality is segmented into separate components: the hypervisor maintains nested page tables for virtual machine memory management, while the IOMMU maintains separate address translation tables specifically for IO device accesses. This segmentation isolates the security-critical IO device access control from the potentially compromised hypervisor address translation.
2Device complexity
If the hypervisor directly controls address translations for virtual machines and IO devices, then system complexity is reduced, but reliability deteriorates due to potential hypervisor corruption or malicious code
Solution Approach 1:
The address translation system is divided into separate hierarchical structures: nested page tables for virtual machine memory management and separate address translation tables in the IOMMU for IO device access control. This segmentation allows independent verification and validation of each translation path, improving reliability without excessive complexity.
Solution Approach 2:
The IOMMU pre-establishes address translation tables that map IO device addresses to specific memory pages allocated to virtual machines. These translation tables are configured in advance with proper access controls, allowing the IOMMU to enforce security policies before any potential malicious or erroneous hypervisor actions can occur.
3Productivity
If address translation caching is implemented to improve IO device performance, then productivity is improved, but security deteriorates because cached translations may be stale or incorrect
Solution Approach 1:
The IOMMU implements a feedback mechanism where address translation entries in the cache are validated against the current state of address translation tables. When the hypervisor modifies memory allocations or address mappings, the IOMMU receives notifications and updates its translation tables accordingly, ensuring cached translations remain accurate and secure.
Solution Approach 2:
The IOMMU pre-validates and caches address translations only after verifying they correspond to properly allocated memory pages with appropriate access permissions. This preliminary validation ensures that cached translations are correct before being used for performance-critical IO device accesses.
Data Source
AI summary
An input-output (IO) memory management unit (IOMMU) uses a reverse map table (RMT) to ensure that address translations acquired from a nested page table are correct and that IO devices are permitted to access pages in a memory when performing memory accesses in a computing device. A translation lookaside buffer (TLB) flushing mechanism is used to invalidate address translation information in TLBs that are affected by changes in the RMT. A modified Address Translation Caching (ATC) mechanism may be used, in which only partial address translation information is provided to IO devices so that the RMT is checked when performing memory accesses for the IO devices using the cached address translation information.