IOMMU Address Translation via CPU TLB Cache Sharing
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Solution Overview
Problem
The existing memory access methods in computer systems are inefficient when handling IOTLB Misses, as they require multiple memory accesses to translate virtual addresses to physical addresses, leading to increased time consumption and reduced I/O performance.
Innovation Solution
A memory access method and apparatus that utilizes an IOMMU to receive memory access requests from PCI devices, search for physical addresses in the IOTLB, and broadcast address probing messages to CPU cores when no match is found, allowing the CPU cores to search in their TLBs and respond with the physical addresses, which are then stored in the IOTLB for subsequent memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the IOMMU queries the process page table in memory to translate virtual addresses to physical addresses when IOTLB Miss occurs, then the address translation can be completed, but the time consumption increases and I/O performance decreases
Solution Approach 1:
The patent merges the IOMMU's IOTLB with the CPU core's TLB resources, allowing the IOMMU to utilize the CPU's TLB cache for address translation when IOTLB Miss occurs. This combination eliminates the need to query the process page table in memory, significantly reducing address translation time while maintaining accurate translation results.
Solution Approach 2:
The patent enables the CPU core's TLB to serve dual purposes: both CPU address translation and IOMMU address translation. By making the TLB universally accessible to both the CPU core and IOMMU, the system avoids duplicate cache structures and reduces the time penalty for IOTLB Miss events.
2Speed
If the IOMMU maintains a separate IOTLB cache, then address translation speed improves, but the device complexity and resource overhead increase
Solution Approach 1:
The patent combines the IOMMU's IOTLB functionality with the CPU core's existing TLB structure. Instead of maintaining a completely separate cache, the IOMMU leverages the CPU's TLB resources, reducing the overall cache memory requirements and simplifying the system architecture while preserving fast address translation capability.
Solution Approach 2:
The TLB is designed to serve multiple functions: CPU virtual address to physical address translation and IOMMU virtual address to physical address translation. This multi-functional design eliminates the need for separate dedicated caches for each function, reducing device complexity and resource overhead.
3Measurement precision
If the IOMMU queries the process page table directly in memory, then address translation can be performed, but the I/O performance and overall system efficiency decrease
Solution Approach 1:
The patent utilizes the TLB cache structure that is preliminarily populated with address translation entries during normal CPU operation. When the IOMMU needs to translate an address, it can immediately query this pre-populated cache rather than performing a full page table walk in memory, significantly improving I/O performance while maintaining translation accuracy.
Solution Approach 2:
The patent merges the IOMMU address translation process with the CPU's existing TLB cache mechanism. By combining these processes, the system leverages the CPU's already-optimized cache structure and population mechanisms, improving I/O performance without sacrificing translation accuracy.
Data Source
AI summary
A memory access method and an input-output memory management unit (IOMMU) are disclosed. The method includes: receiving a memory access request sent by a PCI device, which carrying a virtual address; searching for a physical address corresponding to the virtual address in its IOTLB; in a case that no corresponding physical address is found, broadcasting an address probing message carrying the virtual address to each CPU core; searching for a physical address corresponding to the virtual address in its TLB in response to the address probing message, and sending an address response message carrying the found physical address to the IOMMU after finding the physical address corresponding to the virtual address; and receiving, by the IOMMU, the address response message sent by the CPU core, storing a mapping relationship between the physical address and the virtual address in its IOTLB, and performing memory access based on the physical address.