Ion-Gated Synaptic Transistor for Threshold Voltage Stability
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Solution Overview
Problem
Existing synaptic transistors face challenges in achieving high signal-to-noise ratios due to changes in threshold voltage during manufacturing, and they struggle to simultaneously perform signal processing and learning tasks effectively.
Innovation Solution
A synaptic transistor design that incorporates a substrate, an expansion gate electrode, a gate insulating layer with ions, a channel layer, source and drain electrodes, and a pad electrode, which allows for the movement of hydrogen ions to adjust the threshold voltage and enhance synaptic characteristics, including short-term and long-term memory capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional synaptic transistor structure is used, then the device can perform basic synaptic functions, but the threshold voltage changes during manufacturing process leading to low signal-to-noise ratio
Solution Approach 1:
The patent introduces a retention layer made of insulating material with greater hydrogen bonding force than the gate insulating layer. This retention layer is prepared in advance to compensate for threshold voltage changes that occur during manufacturing, thereby improving the signal-to-noise ratio by preventing voltage drift before it affects device performance.
2Duration of action of stationary object
If the gate insulating layer thickness is increased to improve retention characteristics, then long-term memory capability is enhanced, but the gating effect is reduced
Solution Approach 1:
The patent employs a composite structure consisting of a gate insulating layer and a retention layer with different hydrogen bonding forces. The gate insulating layer provides the gating effect for short-term memory, while the retention layer with stronger hydrogen bonding maintains long-term memory characteristics. This composite material approach allows both functions to coexist without compromising either retention or gating effect.
3Adaptability or versatility
If hydrogen ions are introduced to adjust threshold voltage, then synaptic characteristics are improved, but device complexity increases
Solution Approach 1:
The patent changes the material parameter of the retention layer by selecting insulating materials with greater hydrogen bonding force than the gate insulating layer. This parameter change enables the retention layer to selectively bind hydrogen ions, thereby adjusting the threshold voltage and improving synaptic characteristics such as short-term and long-term memory capabilities without significantly increasing device structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed synaptic transistor achieves a high signal-to-noise ratio by inducing large hysteresis, improves synaptic characteristics through increased gating effect and drain current, and provides both short-term and long-term memory capabilities, enhancing energy efficiency in neuromorphic computing.
Implementation Method 1
the gate insulating layer including ions, covering the expansion gate electrode... when a positive bias is applied to the pad electrode, the ions may move from the side of the pad electrode to the side of the channel layer, or when a negative bias is applied to the pad electrode, the ions may move from the side of the channel layer to the side of the pad electrode
Implementation Method 2
the proposed synaptic transistor achieves a high signal-to-noise ratio by inducing large hysteresis, improves synaptic characteristics through increased gating effect and drain current
Data Source
AI summary
Disclosed is a synaptic transistor, including a substrate, an expansion gate electrode disposed to extend in one direction on the substrate, a gate insulating layer including ions, covering the expansion gate electrode, and disposed on the substrate, a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode, source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer, and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.