3D Logic Circuit Fabrication via Ion Implant Bonding
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in scaling transistor density beyond single-digit nanometer nodes due to manufacturing variability and electrostatic device limitations, prompting the need for three-dimensional integration of semiconductor circuits.
Innovation Solution
The method involves forming multilayer stacks on separate substrates, aligning and bonding them using ionized atom implantation and thermal annealing to create a strong, covalent bond, allowing for the vertical stacking of transistors and increasing transistor density in volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D transistor scaling is continued to increase transistor density, then transistor density per unit area improves, but manufacturing variability and electrostatic device limitations worsen at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangements to three-dimensional vertically stacked transistor configurations. Multiple transistor layers are stacked vertically on top of each other, enabling continued density scaling by utilizing the vertical dimension rather than continuing to scale lateral dimensions where manufacturing variability and electrostatic limitations become prohibitive.
2Quantity of substance
If 2D transistor scaling is continued to increase transistor density, then transistor density per unit area improves, but electrostatic device limitations worsen at single-digit nanometer nodes
Solution Approach 1:
By stacking transistors vertically in the third dimension, the patent achieves higher transistor density without further reducing lateral transistor dimensions. This maintains electrostatic control and device reliability while continuing to scale overall transistor density through vertical integration of multiple transistor layers.
3Quantity of substance
If thermal bonding is used to bond separate nanoplane layer stacks on separate substrates, then transistor density in volume increases, but bonding temperature requirements may conflict with material stability
Solution Approach 1:
The patent introduces bonding films as intermediary layers between the nanoplane layer stacks on separate substrates. These bonding films facilitate thermal bonding at controlled temperatures, enabling vertical stacking and increased volumetric transistor density while protecting the underlying materials from excessive thermal damage through the mediating bonding interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-density 3D logic circuits with increased transistor density, utilizing silicon base area efficiently and achieving effective bonding at low temperatures, thereby overcoming the limitations of two-dimensional scaling.
Implementation Method 1
implanting ionized atoms to a predetermined depth in the first surface of the second substrate
Implementation Method 2
annealing the first substrate and the second substrate to bond the first bonding film with the second bonding film and form a combined structure
Implementation Method 3
annealing also weakening a portion of the second substrate approximately at the predetermined depth of the implanting
Data Source
AI summary
Techniques herein include methods for fabricating high density logic and memory for advanced circuit architecture. The methods can include forming multilayer stacks on separate substrates and forming bonding films over the multilayer stacks, then contacting and bonding the bonding films to form a combined structure including each of the multilayer stacks. The method can be repeated to form additional combinations. In between iterations, transistor devices may be formed from the combined structures. Ionized atom implantation can facilitate cleavage of a substrate destined for growth of additional multilayers, wherein an anneal weakens the substrate at a predetermined penetration depth of the ionized atom implantation.