Ion-Implanted Diffusion Barrier for Semiconductor Metal Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices as feature sizes decrease, leading to increased complexity and issues with metal diffusion during the anneal process, which results in bottom metal loss in connecting structures.
Innovation Solution
A method involving ion implantation to form a diffusion barrier layer within the conductive material, where ions are bonded to the conductive material to obstruct metal diffusion, thereby mitigating the bottom metal loss issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and manufacturing reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by forming a diffusion barrier layer within the conductive material before the anneal process occurs. This pre-formed barrier prevents metal diffusion during subsequent thermal processing, addressing reliability issues before they manifest. The barrier layer is created through ion implantation or deposition steps that prepare the structure in advance to withstand upcoming processing challenges.
Solution Approach 2:
The diffusion barrier layer acts as an intermediary between the conductive material and the anneal process. This intermediate layer prevents direct interaction between the metal and conditions that would cause diffusion, thereby protecting the conductive material while allowing the anneal to proceed for other purposes such as stress relief or dopant activation.
2Reliability
If anneal process is performed to improve device properties, then device performance improves, but metal diffusion occurs causing bottom metal loss
Solution Approach 1:
The patent converts the potentially harmful effect of thermal processing into a beneficial outcome by first creating a diffusion barrier layer through ion implantation. The same thermal anneal that would normally cause metal diffusion is then used to activate the dopants in the barrier layer and enhance its protective properties, while the barrier itself prevents metal loss. The harmful thermal effect is thus transformed into a useful process that strengthens the barrier.
Solution Approach 2:
The diffusion barrier layer serves as an intermediary that allows the anneal process to provide benefits (such as dopant activation and stress relief) while preventing the harmful metal diffusion. The barrier mediates between the thermal processing and the conductive material, enabling useful thermal effects without the detrimental side effects.
3Reliability
If ion implantation is performed to form diffusion barrier layer, then metal diffusion is obstructed, but process complexity increases
Solution Approach 1:
The patent applies local quality by creating a diffusion barrier layer with specific dopant concentrations and compositions only in the regions where metal diffusion is a concern. The ion implantation targets specific areas of the conductive material, providing localized protection rather than uniformly modifying the entire structure. This approach addresses metal diffusion issues precisely where they occur without unnecessarily complicating other areas of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces metal diffusion and maintains the integrity of connecting structures, enhancing the reliability and efficiency of semiconductor device manufacturing.
Implementation Method 1
an implantation is performed after the disposing of the metal layer to form a barrier layer within the conductive material
Implementation Method 2
the dopants are bonded to the metal material in the doped metal portion
Data Source
AI summary
A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.