Ion-Implanted GaN Gate Structure for Leakage Reduction
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Solution Overview
Problem
Conventional GaN transistors face issues with high gate leakage current and reduced efficiency due to sensitive etching requirements and potential rupture of the interface between dielectric and gate sidewalls, limiting maximum voltage application without device destruction.
Innovation Solution
A gate structure is formed with an ion-implanted portion of gate material surrounded by non-implanted GaN, reducing lateral sidewalls and eliminating the need for sensitive etching, while self-aligned gate metal deposition minimizes overlap and capacitance, thereby reducing leakage current and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to define gate boundaries, then gate structure can be formed, but gate leakage current increases and manufacturing precision deteriorates due to sensitive etching requirements and interface rupture
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial mask layer and implanting dopant ions into the gate region before the actual gate formation. This preliminary doping creates a distinct electrical boundary that defines the gate region without requiring sensitive etching, thereby preventing gate leakage current while maintaining manufacturing precision.
Solution Approach 2:
The patent uses a sacrificial mask layer as an intermediary element. This mask layer temporarily defines the gate boundaries during fabrication, allowing precise dopant implantation without direct etching of the gate material. The mask is later removed, leaving a clean interface without rupture, thus reducing gate leakage while maintaining structural integrity.
2Reliability
If gate structure is formed with conventional methods, then device can operate, but breakdown voltage is limited due to interface rupture between dielectric and gate sidewalls
Solution Approach 1:
The patent performs preliminary dopant implantation into the gate region before forming the gate structure. This creates a graded doping profile that strengthens the interface between the gate and dielectric layers, preventing rupture under high voltage stress and thereby increasing breakdown voltage while maintaining device operation.
Solution Approach 2:
The patent changes the electrical parameters of the gate region through controlled ion implantation, creating a dopant concentration gradient. This parameter change strengthens the interface mechanically and electrically, allowing the device to withstand higher breakdown voltages without interface rupture between dielectric and gate sidewalls.
3Ease of operation
If doped epitaxial gate is used, then enhancement mode operation is achieved, but device complexity increases due to additional doping and deposition steps
Solution Approach 1:
The patent merges the gate definition function and the doping function into a single integrated process step. By using a sacrificial mask for both alignment and as a template for ion implantation, the method combines multiple functions (masking, alignment, doping) that would otherwise require separate steps, thereby reducing fabrication process complexity while maintaining enhancement mode operation.
Solution Approach 2:
The sacrificial mask layer serves multiple functions: it defines the gate boundaries, serves as an alignment reference for dopant implantation, and protects adjacent regions during processing. This self-service approach eliminates the need for separate alignment marks and multiple masking steps, reducing device complexity while achieving enhancement mode operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed gate structure significantly reduces gate leakage current and increases gate breakdown voltage, improving device efficiency and power handling without adding complexity or size to the fabrication process.
Implementation Method 1
A gate structure is formed with an ion-implanted portion of gate material surrounded by non-implanted gate material on each side
Data Source
AI summary
A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer.