Ion-Modified Dielectric Removal in Replacement Gate CMOS
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Solution Overview
Problem
The fabrication of advanced integrated circuits using CMOS technology faces challenges in maintaining capacitive coupling and controlling leakage currents due to the use of thin silicon dioxide gate insulation layers, which requires complex patterning and can result in process non-uniformity and variability in transistor performance.
Innovation Solution
The introduction of high-k dielectric materials and stress-inducing dielectric layers, combined with a replacement gate approach where a sacrificial polysilicon material is removed and replaced with a metal-containing electrode, while modifying the interlayer dielectric material through ion bombardment to achieve uniform removal rates and reduce process non-uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thin silicon dioxide gate insulation layers are used to maintain capacitive coupling in scaled transistors, then capacitive coupling is improved, but leakage current increases exponentially
Solution Approach 1:
The patent changes the material parameter of the gate insulation layer from silicon dioxide to high-k dielectric materials (such as hafnium oxide, tantalum oxide, or strontium titanate). This material substitution allows the gate insulation layer to have higher permittivity (k-value), enabling sufficient capacitive coupling even at greater thicknesses, thereby reducing tunneling leakage current while maintaining the required gate-to-channel capacitance for scaled transistor performance
2Speed
If channel length is decreased to improve switching speed and drive current capability, then transistor performance is improved, but short channel behavior increases leakage current
Solution Approach 1:
The patent employs a composite gate structure consisting of a high-k dielectric material layer combined with a metal gate electrode. This composite structure provides enhanced capacitive coupling that compensates for the reduced channel length effects, maintaining strong electrostatic control over the channel region even in aggressively scaled devices, thereby suppressing short channel leakage while preserving high switching speed
3Reliability
If stress-inducing dielectric layers with different internal stress levels are used to enhance transistor performance, then transistor performance is improved, but removal rate uniformity deteriorates
Solution Approach 1:
The patent introduces a placeholder material (such as polysilicon or silicon nitride) as an intermediary sacrificial layer that is deposited over the high-k dielectric material and stress-inducing dielectric layers. This placeholder material serves as a protective intermediary that can be selectively removed later to expose the metal gate electrode, allowing the stress-inducing dielectric layers to remain in place and provide their performance-enhancing stress effects without causing removal rate uniformity issues during processing
4Reliability
If replacement gate approach is used to replace placeholder material with metal-containing electrode, then capacitive coupling is enhanced, but process complexity increases
Solution Approach 1:
The patent performs preliminary actions by first forming the high-k dielectric material layer and the stress-inducing dielectric layers, then depositing a placeholder material over them before metal gate electrode deposition. The placeholder material acts as a temporary protective layer that simplifies subsequent processing by providing a uniform surface for metal deposition and a clear etch selectivity reference, thereby reducing overall process complexity despite the multi-step replacement gate approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by maintaining capacitive coupling and reducing leakage currents, allowing for more flexible circuit design and improved uniformity in transistor fabrication, while avoiding material erosion and contamination issues.
Implementation Method 1
modifying the interlayer dielectric material through ion bombardment to achieve uniform removal rates
Data Source
AI summary
In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.