Ionic Floating Gate Memory for Neuromorphic Computing
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Solution Overview
Problem
Conventional non-volatile memory technologies require high voltages for programming, are difficult to scale beyond binary states, and are ill-suited for neuromorphic computing due to nonlinear programming and coupling of read and write functions, limiting their efficiency and accuracy in large arrays.
Innovation Solution
The Ionic Floating Gate (IFG) memory device, which uses a redox transistor with a switch and solid electrolyte to store ions, allowing for low-voltage operation and linear programmability, enabling multiple states and efficient use in neuromorphic computing with a modified crossbar arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional non-volatile memory elements are used, then binary storage is achieved, but scaling to multiple states is difficult and limited
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage-based charge storage (conventional FLASH) to ion concentration-based storage. The redox transistor channel conducts ions, and by controlling ion concentration through electrochemical reactions, the memory element achieves multiple stable states representing different binary values, enabling scalable multi-state storage without increasing structural complexity
2Reliability
If conventional FLASH memory is programmed, then binary values are stored, but high voltage (approximately 10V) is required which drains battery
Solution Approach 1:
The patent replaces the voltage-based programming mechanism (electrical field injection) with an electrochemical mechanism. A low voltage potential applied to the gate electrode drives electrochemical reactions that transfer ions between the gate and channel, achieving reliable non-volatile storage at much lower voltages suitable for battery-powered devices
3Productivity
If two-terminal devices (RRAM or PCM) are used for neuromorphic computing, then parallel processing is enabled, but read and write functions are coupled causing time-voltage dilemma
Solution Approach 1:
The patent segments the memory element into distinct functional components with separate access paths: the redox transistor handles read operations through its source-drain channel, while the gate electrode independently controls ion transfer for write operations. This three-terminal configuration decouples read and write functions, enabling parallel processing without the time-voltage dilemma inherent in two-terminal devices
4Measurement precision
If RRAM or PCM is used, then analog memory is achieved, but nonlinear programming occurs reducing accuracy for neural network training
Solution Approach 1:
The patent changes the programming mechanism from direct resistance modification (RRAM/PCM) to controlled ion concentration modulation. The electrochemical reactions in the redox transistor channel produce linear changes in ion concentration proportional to the applied gate potential and duration, achieving accurate analog programming essential for neural network weight updates without the nonlinearities that plague conventional analog memory
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The IFG memory device achieves efficient, low-voltage operation with multiple states, suitable for neuromorphic computing, and reduces energy consumption and programming errors, enabling scalable and accurate neural network training.
Implementation Method 1
The solid electrolyte is configured to prevent electrons from passing between the gate electrode and the channel electrode via the solid electrolyte, but allows ions to pass between the gate electrode and channel electrode via the solid electrolyte
Implementation Method 2
the gate electrode is configured to store ions (e.g., positive hydrogen ions), emit ions responsive to electrons being removed from the gate electrode
Implementation Method 3
The IFG memory device comprises a switch that is electrically coupled to a redox transistor. The gate electrode is configured to store ions, emit ions responsive to electrons being removed from the gate electrode, and accept ions responsive to electrons being provided to the gate electrode
Data Source
AI summary
A non-volatile memory device is described herein. The non-volatile memory device includes a diffusive memristor electrically coupled to a redox transistor. The redox transistor includes a gate, a source, and a drain, wherein the gate comprises a first storage element that acts as an ion reservoir, and a channel between the source and the drain comprises a second storage element, wherein a state of the memory device is represented by conductance of the second storage element.