IOSA Latch Enable Control for Extended Memory Test Windows
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in safely testing the characteristics of input/output sense amplifiers (IOSAs), as they typically only test valid data and fail to account for invalid data and noise signals, leading to test errors due to the limited pulse duration of latch enable signals.
Innovation Solution
An IOSA control circuit is introduced, featuring an auto pulse generator and a latch enable signal generating circuit that produces a second latch enable signal with a level shape during test mode, allowing for the activation of the latch during both valid and invalid data intervals, ensuring comprehensive testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional auto pulse generator with first pulse shape is used to control the IOSA latch enable signal, then the IOSA can operate in normal mode, but the testing of invalid data and noise signals is insufficient leading to test errors
Solution Approach 1:
The latch enable signal generating circuit dynamically changes the pulse shape of the latch enable signal based on the test mode signal. In test mode, it generates a second pulse shape with extended high level duration to enable comprehensive testing of valid data, invalid data, and noise signals. This dynamic adaptation resolves the contradiction by making the testing system versatile enough to cover all data types while maintaining reliable operation.
Solution Approach 2:
The invention changes the temporal parameters of the latch enable signal by generating a second pulse shape with a longer high level duration compared to the conventional first pulse shape. This parameter change allows the latch to remain enabled during extended periods, enabling the testing of invalid data and noise signals that occur outside the normal valid data window, thereby improving testing coverage without sacrificing reliability.
2Adaptability or versatility
If the pulse duration of the latch enable signal is increased to test invalid data, then testing coverage improves, but the risk of testing errors increases due to extended activation during invalid data periods
Solution Approach 1:
The latch enable signal generating circuit applies different pulse shapes (different qualities) to different testing scenarios. The second pulse shape is specifically designed with extended duration localized to the test mode operation, while normal operation continues to use the conventional first pulse shape. This local differentiation allows extended testing coverage during invalid data periods without compromising the reliability of normal operations.
Solution Approach 2:
The latch enable signal generating circuit acts as an intermediary between the auto pulse generator and the IOSA latch. It receives the conventional auto pulse signal and transforms it into an appropriate latch enable signal based on the test mode signal. This intermediary function allows the system to extend pulse duration for comprehensive testing while maintaining proper signal integrity and preventing test errors through controlled signal transformation.
3Device complexity
If a conventional IOSA control circuit is used, then the device structure remains simple, but comprehensive testing of IOSA characteristics including invalid data and noise signals cannot be performed
Solution Approach 1:
The latch enable signal generating circuit is designed with multi-functionality to handle both normal operation and comprehensive testing requirements. It responds to the test mode signal to generate appropriate pulse shapes, enabling the same circuit to support both valid data operation and extended testing of invalid data and noise signals. This universality increases testing capability without requiring separate dedicated testing hardware, thus managing device complexity effectively.
Data Source
AI summary
An input/output sense amplifier (IOSA) controller of a semiconductor memory device includes an auto pulse generator and a latch enable signal generating circuit. The auto pulse generator generates an auto pulse signal having a first pulse shape. The latch enable signal generating circuit generates a first latch enable signal having a second pulse shape in response to an auto pulse signal in normal mode, and generates a second latch enable signal having a level shape that is enabled for long duration in response to the write enable bar signal in test mode. Accordingly, the semiconductor memory device including the IOSA controller may safely test a characteristic of the IOSA.