Unified IP-Core Abstraction for SoC Verification
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Solution Overview
Problem
The complexity and size of modern system-on-chip (SoC) designs, incorporating multiple functional blocks and third-party intellectual property cores, make full chip verification difficult due to resource and time constraints, with existing methods being inefficient in capturing and correcting design issues like clock domain crossing and structural connectivity.
Innovation Solution
A computer-implemented method generates unified abstracted views of intellectual property cores, tagged with verification-specific attributes, allowing for efficient verification of SoC designs across various verification types, reducing redundant attributes and integrating unique ones for comprehensive verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full chip verification methods are used to verify SoC designs with multiple functional blocks and third-party IP-cores, then verification completeness is improved, but verification time and resource consumption increase excessively
Solution Approach 1:
The patent segments the SoC verification process into hierarchical levels, separating third-party IP-cores from the main SoC design. IP-cores are verified independently using their own verification environments, while the SoC level performs integration verification. This segmentation allows complete verification without requiring full chip simulation, resolving the time-completeness contradiction.
Solution Approach 2:
The patent introduces an intermediary abstraction layer between the SoC design and third-party IP-cores. This intermediary interface model captures only the necessary interaction characteristics without exposing internal IP-core complexities. The intermediary enables verification of SoC integration effects while avoiding the resource-intensive full verification of IP-cores.
2Adaptability or versatility
If third-party IP-cores are integrated into SoC designs, then functional capability is improved, but integration complexity increases due to unknown internal functionality
Solution Approach 1:
The patent extracts the verification and validation responsibilities from the SoC design team and places them with the third-party IP-core providers. Each IP-core comes with its own verification documentation and interface models that capture essential characteristics. This extraction reduces integration complexity by removing the need to understand internal IP-core functionality while maintaining functional capability.
Solution Approach 2:
The patent creates a universal interface modeling approach that works for all third-party IP-cores regardless of their internal implementation. The same abstraction methodology applies to different IP-core types, enabling standardized integration verification. This universality reduces complexity by providing a single approach for handling diverse IP-cores.
3Quantity of substance
If hierarchical abstraction is applied to reduce verification resources, then resource consumption is reduced, but verification precision may be compromised
Solution Approach 1:
The patent applies local quality by maintaining different levels of detail at different verification stages and locations. At the IP-core level, detailed verification is performed with full precision. At the SoC integration level, abstraction is applied to reduce resources, but precision is maintained through careful interface modeling that captures all critical interaction characteristics. This localized approach ensures precision where needed while saving resources where appropriate.
Data Source
AI summary
In order to realize some of the advantages described above, there is provided a computer system for verification of an intellectual property (IP) core in a system-on-chip (SoC). The system generates a plurality of verification specific abstracted views of the IP core, each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view of the IP-core is generated.