Incremental Compile Flow for IP Core Placement and Routing
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Solution Overview
Problem
Existing methods for implementing intellectual property (IP) cores on field programmable gate arrays (FPGAs) often result in suboptimal performance due to generic placement and routing, as IP cores are typically delivered in compiled form without considering user-specific requirements or registered boundaries, leading to inefficiencies in resource allocation and design customization.
Innovation Solution
The method involves delivering IP cores as uncompiled source code and partitioning the IP section to include registered boundaries, allowing for incremental compilation that prioritizes synthesis, placement, and routing to meet user-specific requirements, ensuring optimal resource allocation and performance by compiling the IP section separately before the remaining system partitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If IP cores are delivered in compiled form with generic placement and routing, then ease of manufacture is improved, but device performance and adaptability deteriorate
Solution Approach 1:
The design flow is segmented into distinct phases: IP core compilation, user logic compilation, and final integration. The IP core is compiled separately with placeholder representations, allowing independent optimization of placement and routing for the IP section before integrating with user logic. This segmentation enables customized placement and routing for each component while maintaining ease of manufacture through automated compilation processes.
2Ease of manufacture
If IP cores are delivered in compiled form with generic placement and routing, then ease of manufacture is improved, but adaptability to user-specific requirements deteriorates
Solution Approach 1:
The compilation process is made dynamic by allowing different compilation strategies for different sections of the design. The IP core section can be compiled with specific placement and routing constraints tailored to user requirements, while the overall system maintains ease of manufacture through automated incremental compilation. The placeholder representation mechanism enables flexible adaptation without requiring complete recompilation.
3Reliability
If incremental compilation is used to compile IP section separately, then device performance is improved, but device complexity increases
Solution Approach 1:
Placeholder representations act as intermediaries between the IP core compilation process and the final integrated design. These placeholders allow the IP section to be compiled and optimized independently with specific placement and routing, improving device performance. The placeholders automatically manage the complexity of integration by providing a standardized interface between the IP section and user logic, reducing the overall device complexity.
4Measurement precision
If registered boundaries are added to IP core interfaces, then timing precision is improved, but device complexity increases
Solution Approach 1:
Registered boundaries are applied locally at the interfaces of the IP core rather than throughout the entire design. This local application of registration improves timing precision at critical interfaces where the IP core connects to user logic. The incremental compilation process automatically manages the complexity of adding these registered boundaries by only affecting the IP section and its immediate interfaces, leaving the rest of the design unchanged.
Data Source
AI summary
A method for designing a system on a target device includes compiling an intellectual property (IP) core to be implemented on the target device such that it satisfies user specified requirements for the system. User logic is compiled after the IP core has been compiled to satisfy user specified requirements for the system.