Mid-Level IP Core Modeling for IC Performance Estimation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional IC design tools lack effective methods to estimate how user-selected parameters of intellectual property cores, such as the number of taps in an FIR filter, affect system performance, leading to difficulties in resource allocation, power consumption, delay, and latency, due to limited information and time-consuming simulation processes.
Innovation Solution
A method using mid-level IP core component modeling to pre-characterize performance characteristics, creating a library of estimation calculations for various parameter sets, and deriving resource equations through curve-fitting, allowing for quick estimation of performance across different IC technologies and families without running the entire design tool.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If conventional tabular methods are used to provide IP core parameter information, then documentation is provided to designers, but the methods are difficult to use and error-prone when dealing with complex IP cores having millions of parameter combinations
Solution Approach 1:
The patent creates simplified copies of the complex IP core parameter relationships through graphical visualizations. Instead of presenting raw tabular data with millions of combinations, the system generates graphical representations that copy the essential relationships between parameters and resources, making the information both complete and easily usable by designers.
Solution Approach 2:
The patent transforms one-dimensional tabular data into multi-dimensional graphical visualizations. By adding visual dimensions such as graphs, charts, and interactive displays, the system enables designers to comprehend complex parameter relationships that would be impossible to interpret from traditional tables alone.
2Measurement precision
If complete tool flow is run for each parameter change to evaluate IC design implementation, then accurate performance evaluation is achieved, but the process is time-consuming and tedious
Solution Approach 1:
The patent performs preliminary characterization of IP cores by pre-running complete tool flows for a representative set of parameter combinations. These pre-computed results are stored and can be quickly queried during design exploration, eliminating the need to run full simulations for every parameter change while maintaining accuracy.
Solution Approach 2:
The patent uses partial tool flow executions combined with graphical estimation methods. Instead of running complete implementations for all parameter evaluations, the system performs partial analyses on selected parameters and uses graphical visualizations to estimate and interpolate results for other parameter combinations, significantly reducing computation time while maintaining sufficient accuracy.
3Ease of operation
If only a few parameters are provided in graphical form as in conventional tools, then some visualization is achieved, but comprehensive parameter analysis is not possible
Solution Approach 1:
The patent creates a universal graphical analysis framework that can handle multiple IP core types and parameter combinations through a single integrated system. The methodology is designed to work with any IP core (FIR filters, FFTs, memory generators, etc.) and any parameter set, providing comprehensive visual analysis capabilities rather than being limited to specific cases.
Solution Approach 2:
The patent implements dynamic graphical visualizations that can adapt to show different parameter relationships based on user needs. The system can dynamically generate and switch between different graphical representations (resource vs. latency, resource vs. power, etc.) and adjust the displayed parameters based on what the designer wants to explore, providing versatile analysis capabilities.
Data Source
AI summary
A method (100) of estimating a performance characteristic of an integrated circuit (IC) design having an intellectual property (“IP”) core pre-characterizes an element type of the IC design to provide an estimation result of the element type (102-108). Mid-level elements of the IP are acquired (116). A user selects a value of a parameter of the IP core and the IC design is run on a design tool using the estimation result to model the mid-level elements of the IP core (118) to return a performance value of the IC design (120).