IP Integrity Checker Modules for SOC Interconnect Verification
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Solution Overview
Problem
The integration of third-party IP modules into System-On-Chip (SOC) designs poses a risk of compromising IP functionality due to potential interconnection violations, which are difficult to detect using system-level functional simulation, and formal equivalence verification tools require significant investment and knowledge of the IP structure.
Innovation Solution
A method and system for verifying IP integrity by partitioning IP designs into modules, providing corresponding integrity checker modules that are simulated within the user's design to validate interconnections and generate a verification report, eliminating the need for costly simulations and deep knowledge of the IP structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If formal equivalence verification tools are used to verify IP integrity, then verification accuracy is improved, but tool complexity and knowledge requirement increase
Solution Approach 1:
The patent creates a copy of the IP module called an Integrity Checker Module (ICM) that has the same interface and structure as the original IP module. This copy is used to verify interconnections without requiring complex formal equivalence verification tools, thus maintaining verification accuracy while reducing tool complexity
Solution Approach 2:
The ICM acts as an intermediary between the IP module and the SOC design. It receives signals from the IP module outputs and compares them with expected values, providing a simple mediation mechanism that avoids the need for complex verification tools
2Ease of operation
If system-level functional simulation is used to detect interconnection violations, then ease of operation is improved, but detection capability deteriorates
Solution Approach 1:
The verification process is segmented into two independent parts: the original IP module functionality and the integrity checking functionality. The ICM is a separate module that specifically checks interconnections, allowing simple system-level simulation while improving detection capability for interconnection violations
Solution Approach 2:
The ICM changes the signal characteristics (analogous to color changes) by comparing output signals with expected values. When a violation occurs, the signal state changes to indicate the error, making it detectable during simple functional simulation without requiring complex analysis
3Adaptability or versatility
If IP modules are partitioned into separate modules for integration, then adaptability is improved, but verification difficulty increases
Solution Approach 1:
The IP module is segmented into functional sub-modules that can be independently integrated into the SOC design. Each segment can be verified using its corresponding ICM, maintaining integration flexibility while simplifying verification through modular checking
Solution Approach 2:
The ICM serves multiple functions: it verifies interconnection integrity, validates signal transitions, and ensures proper module integration. This multi-functionality reduces verification difficulty by consolidating multiple verification tasks into a single simple simulation process
Data Source
AI summary
An intellectual property (IP) integrity verification system and method operable with respect to integrating an IP design into a user's embedded IC design. In one embodiment, the IP design is partitioned into a plurality of IP modules based on the requirements of the embedded IC design. For each IP module, a corresponding integrity checker module is provided, wherein each integrity checker module has a port-wise correspondence with its corresponding IP module. The embedded IC design is simulated with the integrity checker modules rather than the IP modules for generating a netlist, which may be verified with respect to any interconnectivity errors associated with the IP modules.