IP Stream Receiver Timing Synchronization via TS Timestamps
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Solution Overview
Problem
Existing IP stream receiving systems face challenges in maintaining stable processing timing and error correction efficiency, particularly under unstable network conditions such as jitter and packet loss, which limits the effectiveness of FEC decoding processes like LDPC.
Innovation Solution
The system generates receiving processing timing based on TS synchronization established through TS time stamp reproducing processing at a latter stage of FEC decoding, using a temporary synchronizing timing for initial error correction and transitioning to block synchronization for stable FEC input, correction, and output processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If receiving processing timing is generated based on network packet arrival time, then the system can adapt to variable network conditions, but processing timing becomes unstable under network jitter and packet loss
Solution Approach 1:
The patent applies preliminary action by establishing TS synchronization through time stamp reproducing processing before FEC decoding. The receiving device pre-synchronizes with the transmitting side using TS packets and time stamps, then maintains this synchronization throughout FEC input, correction, and output processing. This preliminary synchronization action ensures stable processing timing even when network conditions cause jitter or packet loss, as the device continues to reference the pre-established synchronization rather than reacting to variable packet arrival times.
2Productivity
If FEC decoding is performed with limited processing time, then real-time processing is achieved, but error correction efficiency deteriorates under unstable network conditions
Solution Approach 1:
The patent implements feedback by continuously monitoring TS synchronization status and using it to regulate FEC decoding timing. The receiving device establishes TS synchronization, then feeds this synchronization information back to control the timing of FEC input processing, correction processing, and output processing. This feedback mechanism ensures that each FEC processing stage occurs at the correct synchronized timing, maintaining both real-time processing speed and high error correction efficiency even under unstable network conditions.
3Manufacturing precision
If processing timing is synchronized with transmitting side, then processing accuracy is improved, but system complexity increases due to synchronization requirements
Solution Approach 1:
The patent uses TS packets and time stamps as intermediaries to establish synchronization between transmitting and receiving devices. Rather than implementing complex direct synchronization protocols, the device uses the existing TS packet structure with embedded time stamps as an intermediary mechanism. The receiving device extracts time stamps from TS packets, reproduces the transmitting side's timing information, and uses this intermediary synchronization reference to control FEC processing timing, thereby achieving high processing accuracy without excessive system complexity.
Data Source
AI summary
An IP (Internet Protocol) stream transmitting/receiving system according to an exemplary aspect of the present invention is an IP stream transmitting/receiving system including an IP stream receiving device for performing, at a receiving processing timing of an IP stream, at least FEC (Forward Error Correction) decoding of a received IP stream, wherein the IP stream receiving device includes a circuit for generating the receiving processing timing based on TS (Transport Stream) synchronization that is established in TS time stamp reproducing processing at the latter stage of the FEC decoding processing.