Inter-Processor Communication Unit With Doorbell Registers
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Solution Overview
Problem
Current artificial reality systems face challenges in efficient inter-processor communication, leading to increased latency and power consumption due to the need for direct communication between source and target CPUs, which is not optimized for interrupt prioritization and shared resource management.
Innovation Solution
The implementation of a System-on-Chip (SoC) integrated circuit with a network-on-chip (NoC) and an inter-processor communication (IPC) unit that utilizes doorbell registers and doorbell FIFO memories to facilitate interrupt requests and message passing between processors, allowing for efficient interrupt prioritization and reducing the need for direct CPU communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If direct communication between source and target CPUs is used, then inter-processor communication is established, but latency increases and power consumption increases
Solution Approach 1:
The patent introduces an inter-processor communication (IPC) unit as an intermediary component that mediates communication between source and target processors. The IPC unit includes doorbell registers and doorbell FIFO memories that buffer data and control interrupt requests, eliminating the need for direct CPU-to-CPU communication and reducing both latency and power consumption.
Solution Approach 2:
The communication system is segmented into distinct functional components: source processor, IPC unit with doorbell registers and FIFO memories, and target processor. This segmentation allows each component to perform its specific function efficiently, with the IPC unit handling data buffering and interrupt management separately from the processors.
2Productivity
If optimized interrupt prioritization and shared resource management are implemented, then communication efficiency is improved, but device complexity increases
Solution Approach 1:
The IPC unit serves multiple functions within a single integrated component: it manages doorbell registers for interrupt requests, maintains doorbell FIFO memories for data buffering, handles interrupt prioritization, and manages communication between multiple processor pairs. This multi-functionality improves communication efficiency without proportionally increasing system complexity.
Data Source
AI summary
The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors and an inter-processor communication (IPC) unit. The IPC unit includes one or more doorbell registers, wherein each doorbell register is associated with a uniquely assigned source processor and a uniquely assigned target processor. Each doorbell register is further configured to store doorbell data indicative of whether an interrupt is a high priority interrupt or a low priority interrupt. The IPC unit may also include one or more FIFO (first-in first-out) memories configured to store data associated with each interrupt.