Inter-Processor Communication Link for Low-Latency Data Transfer
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Solution Overview
Problem
Existing inter-processor communication technologies like PCIe are unsuitable for portable consumer electronics due to high power consumption and limited power management, failing to support low latency and low power requirements for applications like Bluetooth, which necessitate efficient data transfer while allowing processors to operate in various sleep states.
Innovation Solution
The implementation of an inter-processor communication (IPC) link that selects transmission modes based on application constraints, such as power, latency, and throughput, using protocols like Bluetooth or HCI, allowing payloads to be transmitted directly or through external memory, and utilizing doorbell messages to optimize data transfer without external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PCIe technology is used for inter-processor communication, then data throughput is improved, but power consumption increases and latency cannot be reduced sufficiently
Solution Approach 1:
The patent implements multiple transmission modes (first transmission mode using external memory, second transmission mode using direct payload placement in data structure) that can be dynamically selected based on application constraints such as power consumption requirements and latency requirements. This allows the system to adapt between throughput-optimized mode and power-efficient mode, resolving the contradiction between high data throughput and low power consumption.
Solution Approach 2:
The patent changes the parameter of data transmission architecture by introducing a hybrid approach that can switch between two distinct transmission pathways: one through external memory (PCIe-like) and one through direct payload placement in data structures. This parameter change enables the system to achieve both high throughput when needed and low power consumption when sufficient, eliminating the fixed trade-off in traditional PCIe implementations.
2Productivity
If PCIe technology is used for inter-processor communication, then data transfer capability is improved, but latency increases due to external memory access requirements
Solution Approach 1:
The patent implements preliminary action by placing payloads directly into designated portions of data structures (such as transfer descriptors) before transmission in the second transmission mode. This eliminates the need for receiving processors to perform separate external memory accesses to retrieve payload data, thereby reducing latency while maintaining data transfer capability. The payload is prepared in advance in the correct location, ready for immediate processing.
Solution Approach 2:
The patent extracts the payload from the external memory access path and places it directly within the data structure (transfer descriptor) that is transmitted over the inter-processor link. This extraction eliminates the mandatory external memory access step that causes latency in traditional PCIe implementations, allowing the receiving processor to obtain both the descriptor and payload in a single operation.
3Device complexity
If traditional inter-processor communication is used, then system simplicity is maintained, but adaptability to different application constraints (power, latency, throughput) is limited
Solution Approach 1:
The patent implements universality by designing the inter-processor communication system to perform multiple functions through a unified architecture. The same inter-processor link and data structures can operate in different transmission modes (first mode with external memory, second mode with direct payload placement) depending on application constraints. This multi-functionality allows the system to adapt to varying power, latency, and throughput requirements without requiring separate specialized interfaces for each constraint.
Solution Approach 2:
The patent introduces dynamics by enabling the system to switch between different transmission modes based on runtime conditions and application constraints. The selector can choose between the first transmission mode (optimized for throughput) and the second transmission mode (optimized for power efficiency and latency) dynamically, allowing the simple unified architecture to adapt to diverse application requirements without compromising system simplicity.
Data Source
AI summary
Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.