Inter-Processor Communication Link Power Management
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Solution Overview
Problem
Existing PCIe technologies consume significant power and lack effective power management, making them unsuitable for portable consumer electronics, and are unable to accommodate scenarios where the peripheral processor operates while the host processor is asleep or vice versa, which is common in devices like cellular devices and media players.
Innovation Solution
An inter-processor communication (IPC) link is established between independently operable processors using a shared memory interface for run-time processing, enabling host-assisted boot sequencing and supporting various operational sleep states, with power management schemes that allow the IPC link to remain functional even when one processor is asleep, and error handling mechanisms to ensure reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PCIe technology is used for inter-processor communication, then data throughput and bus performance are improved, but power consumption increases significantly
Solution Approach 1:
The system segments the communication interface into two modes: PCIe mode for high-performance data transfer when both processors are active, and IPC mode for low-power communication when one processor is in sleep state. This segmentation allows the system to use the appropriate interface based on operational requirements, reducing overall power consumption while maintaining data throughput when needed.
Solution Approach 2:
The system dynamically switches between PCIe and IPC communication modes based on the power states of the processors. When both processors are active, PCIe mode is used for high throughput; when one processor enters sleep state, the system transitions to IPC mode over shared memory, which consumes less power. This dynamic adaptation resolves the contradiction between maintaining performance and reducing power consumption.
2Ease of operation
If traditional PCIe architecture is used, then host processor control is simplified, but the system cannot accommodate scenarios where peripheral processor operates while host processor is asleep
Solution Approach 1:
The shared memory interface serves multiple functions: it acts as cache memory during normal operation, provides communication channel during PCIe mode, and enables IPC mode when processors are in different power states. This multi-functionality allows the system to maintain ease of operation through unified memory access while adapting to various operational scenarios including asymmetric power states.
Solution Approach 2:
The shared memory interface acts as an intermediary between the host and peripheral processors, enabling communication and coordination when processors are in different power states. It mediates the boot sequencing process and facilitates data transfer without requiring the host processor to be fully active, thus improving adaptability while maintaining operational simplicity.
3Speed
If PCIe link is used, then communication speed between processors is improved, but the link becomes non-functional when one processor enters sleep state
Solution Approach 1:
The system maintains continuous communication capability by transitioning from PCIe link to IPC mode over shared memory when one processor enters sleep state. The shared memory remains accessible to both processors regardless of their power states, ensuring that communication continues without interruption. This continuity resolves the contradiction by maintaining link functionality across different operational states while preserving communication speed through efficient memory access.
Data Source
AI summary
Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.