Inter-Processor Communication Reordering via Descriptor Rings
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Solution Overview
Problem
Existing inter-processor communication (IPC) technologies face challenges in efficiently re-ordering out-of-order data packets in mobile devices, which require significant memory resources due to higher bandwidth, leading to memory constraints and increased power consumption.
Innovation Solution
A method and apparatus for re-ordering out-of-order data transactions over an IPC link between independently operable processors, involving the use of transfer descriptors and completion descriptors to determine and provide the correct order, allowing for efficient re-transmission and re-ordering of packets, thereby reducing memory requirements and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional IPC technologies are used to handle higher data rates and data throughput, then data transmission capability is improved, but memory requirements increase significantly
Solution Approach 1:
The patent segments data transactions into groups and uses transfer descriptors to manage individual packet ordering within those groups. This allows the system to achieve high throughput while reducing the memory footprint by only tracking order information for packets that need reordering, rather than buffering all packets individually.
Solution Approach 2:
The patent introduces transfer descriptors and completion descriptors as intermediary data structures that mediate between the data transmission and reordering operations. These descriptors carry ordering information and enable the system to re-order packets without requiring large memory buffers, thus resolving the contradiction between throughput and memory requirements.
2Reliability
If out-of-order data packets are re-ordering is performed to ensure data integrity, then data processing accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies partial reordering by only re-ordering packets within groups that contain out-of-order arrivals, rather than re-ordering all packets sequentially. This selective approach maintains data integrity for affected packets while minimizing the power consumption associated with comprehensive reordering operations.
Solution Approach 2:
The patent changes the parameter of packet grouping, organizing data transactions into groups that can be processed together. This allows the system to maintain reliability through targeted reordering within groups while reducing overall power consumption by avoiding unnecessary reordering operations across the entire data stream.
3Adaptability or versatility
If memory requirements are reduced to address mobile device constraints, then device adaptability is improved, but data reordering capability deteriorates
Solution Approach 1:
The patent extracts the essential reordering information into transfer descriptors and completion descriptors, separating the ordering logic from the data buffering requirements. This extraction allows the system to maintain reordering capability with minimal memory, as only the descriptor structures need to be stored rather than all packet data.
Solution Approach 2:
The patent moves the reordering operation from a time-based sequential process to a space-based parallel process by using descriptor rings and completion groups. This dimensional change allows multiple packets to be tracked and reordered simultaneously with reduced memory footprint, improving device adaptability without sacrificing reordering capability.
Data Source
AI summary
Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.