IPC Scheduler Batching Non-Real-Time Tasks

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Solution Overview

Problem

In computer systems, particularly in mobile devices, there is a challenge in balancing processing power with power consumption, as increasing processing power leads to higher energy usage, and frequent transitions between sleep and awake modes in processors consume significant latency and energy during inter-processor communication (IPC) activities.

Innovation Solution

Implementing a scheduler that identifies non-real-time sensitive IPC activities and delays them to group them together for communication during a continuous awake phase of the processor, reducing the number of times the processor needs to enter and exit sleep mode, thereby minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the processor operates in awake mode to process IPC activities, then processing capability is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

The processor alternates between awake mode and sleep mode in periodic cycles. IPC activities are scheduled during awake periods, then the processor returns to sleep mode. This periodic operation allows the system to maintain processing capability when needed while minimizing power consumption during idle periods, directly resolving the contradiction between processing power and energy usage.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The scheduler identifies and queues IPC activities in advance before the processor enters sleep mode. By preparing the task queue beforehand and knowing which activities are real-time sensitive versus non-real-time sensitive, the system can efficiently wake up only when necessary and process predetermined tasks, reducing unnecessary wake-ups and optimizing the balance between processing capability and power consumption.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the processor wakes up frequently to process individual IPC activities, then communication responsiveness is improved, but latency increases

Engineering Contradiction:
Improvecommunication responsivenessVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Multiple IPC activities are merged into single wake-up events. The scheduler groups non-real-time sensitive IPC activities and batches them together, so the processor wakes up once to handle multiple tasks rather than waking up separately for each activity. This merging reduces the frequency of mode transitions and minimizes cumulative latency while maintaining communication responsiveness.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The scheduler acts as an intermediary between incoming IPC activities and the processor. It buffers and manages the queue of IPC tasks, determining optimal wake-up times and grouping activities appropriately. This intermediary layer decouples the immediate arrival of IPC messages from the processor's wake-up schedule, reducing latency caused by frequent mode transitions while preserving communication responsiveness.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If the processor enters sleep mode to conserve power, then power consumption is reduced, but processing delay increases

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing delay
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system applies different quality standards to different IPC activities based on their real-time sensitivity. Real-time sensitive activities receive immediate processing with higher priority, while non-real-time sensitive activities are deferred and batched. This local differentiation allows the processor to enter sleep mode more frequently for power savings while ensuring that time-critical tasks are handled with minimal delay.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The scheduler dynamically changes the operational parameters of the processor, switching between awake and sleep modes based on the current workload and the real-time sensitivity of pending IPC activities. By adjusting the wake-up frequency and timing parameters according to task urgency, the system optimizes the trade-off between power consumption and processing delay, entering sleep mode when safe to do so and waking up when necessary.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9329671B2Power-efficient inter processor communication scheduling
Publication Date: 2016.05.03 NVIDIA CORP
  • US9329671B2 patent drawing
  • US9329671B2 patent drawing
  • US9329671B2 patent drawing

AI summary

Computer system, method and computer program product for scheduling IPC activities are disclosed. In one embodiment, the computer system includes first processor and second processors that communicate with each other via IPC activities. The second processor may operate in a first mode in which the second processor is able to process IPC activities, or a second mode in which the second processor does not process IPC activities. Processing apparatus associated with the first processor identifies which of the pending IPC activities for communicating from the first processor to the second processor are not real-time sensitive, and schedules the identified IPC activities for communicating from the first processor to the second processor by delaying some of the identified IPC activities to thereby group them together. The grouped IPC activities are scheduled for communicating to the second processor during a period in which the second processor is continuously in the first mode.