Two-Layered IPC Scheduler for SSD I/O Determinism

The patent divides the storage system into multiple NVM sets (non-volatile memory sets), where each NVM set can be independently accessed by different applications. This segmentation isolates I/O operations into separate queues, preventing one application from interfering with another's latency, thus maintaining predictable I/O performance while allowing multiple applications to share the overall storage resources.

The patent introduces a temporal dimension to data transfer by implementing a scheduling system that alternates between different NVM sets in time slices. While the memory bus handles one device at a time, the scheduler rapidly switches between multiple NVM sets, effectively parallelizing the throughput across applications without compromising the integrity of individual transfers.

The patent introduces an intermediary scheduling layer between the host applications and the NAND flash memory devices. This scheduler receives I/O requests from multiple unsynchronized applications, orders them according to a deterministic scheduling algorithm (such as round-robin or priority-based scheduling), and ensures that each application receives predictable I/O latency regardless of when it submits requests.

The patent segments the address space into multiple NVM sets, each independently addressable by different applications. The controller implements corresponding segmented queues and scheduling logic, where each NVM set has its own I/O queue. This segmentation approach manages complexity by organizing the controller around clear, modular boundaries rather than requiring complex arbitration for shared resources.