IPD Testing via DTS Module for Thermal Mismatch Reliability

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Solution Overview

Problem

The integration of integrated passive devices (IPDs) with other circuits or die in semiconductor packages often results in low-reliability devices due to mismatched coefficients of thermal expansion, leading to structural damage and reliability issues in high-frequency applications like RF systems.

Innovation Solution

A diagnosis test solution (DTS) module is introduced to perform pass/fail determination of IPDs attached to integrated circuits on product wafers, using a probe card with RF probes and a DTS module that generates test signals and receives responses, allowing for testing of IPDs without affecting the SoC die, and optionally includes a redundant DTS module for fault tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If IPDs are integrated with SoC die in semiconductor packages, then functionality is improved, but reliability deteriorates due to thermal expansion mismatch

Engineering Contradiction:
ImprovefunctionalityVSAvoidreliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements preliminary testing of IPDs using a DTS module before final package assembly. The test system applies test signals to IPDs on the wafer and measures responses to identify defective devices early, preventing unreliable IPDs from being integrated into the final semiconductor package. This preliminary action ensures only reliable IPDs are combined with SoC die, resolving the reliability issue while maintaining functionality integration.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If multiple IPDs are combined in semiconductor packages, then system functionality is improved, but difficulty of detecting and measuring individual IPD performance worsens

Engineering Contradiction:
Improvesystem functionalityVSAvoidIPD performance measurement
Core Design Contradiction:
Adaptability or versatilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent segments the testing process by isolating individual IPDs for measurement. The DTS module connects to specific IPDs on the wafer through probe cards, allowing independent testing of each IPD's electrical characteristics. This segmentation enables precise measurement of individual IPD performance (such as capacitance, inductance, or resistance) even when multiple IPDs are present in the package, resolving the measurement difficulty while maintaining system functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a DTS module as an intermediary testing system between the IPDs and the test equipment. This intermediary module generates test signals, interfaces with IPDs through probe cards, and processes responses to determine IPD performance. The intermediary enables indirect but accurate measurement of IPD characteristics without requiring direct access to each component, solving the measurement challenge in multi-IPD configurations.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If IPDs are tested after integration with SoC die, then device completeness is improved, but testing complexity and potential damage risk worsen

Engineering Contradiction:
Improvedevice completenessVSAvoidtesting complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent performs IPD testing before final integration with SoC die by testing IPDs while they are still on the wafer. The DTS module applies test signals to IPDs through probe cards in a preliminary testing stage, identifying defective IPDs before they are assembled into complete semiconductor packages. This preliminary testing reduces overall testing complexity by eliminating the need for complex post-integration testing and prevents potential damage to already-assembled devices.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9859176B1Semiconductor device, test system and method of the same
Publication Date: 2018.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9859176B1 patent drawing
  • US9859176B1 patent drawing
  • US9859176B1 patent drawing

AI summary

A semiconductor device is disclosed. The semiconductor device includes: a System on Chip (SoC) die; an integrated passive device (IPD); and a first switch, coupled between the SoC die and the IPD; wherein the IPD and the SoC die are disposed in different wafers and bonded together, and the first switch is controlled to disconnect the IPD from the SoC die when the IPD is under a test; and the first switch is controlled to connect the IPD with the SoC die when the IPD is not under the test. A test system for testing an IPD of a semiconductor device and an associated method are also disclosed.