Integrated Passive Device System for High Q Inductors
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Solution Overview
Problem
The miniaturization of radio frequency (RF) circuits is hindered by the difficulty in producing suitable inductors and capacitors in silicon technologies, with inductor Q values less than five and size and tolerance issues, and the use of special metalization layers is costly and not acceptable for integrated circuit products.
Innovation Solution
An integrated passive device system is formed by creating a first dielectric layer over a semiconductor substrate, depositing a metal capacitor layer, and adding a second dielectric layer with a metal layer to produce integrated capacitors, resistors, and inductors, utilizing materials like silicon dioxide, tantalum silicide, and copper to achieve high Q factor inductors and capacitors with values less than 1 pF.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wide metal line-widths are used to reduce DC resistance, then inductor Q is improved, but inductor area increases and parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar metal line inductors to three-dimensional spiral inductor structures with vertical stacking. Multiple metal layers are stacked vertically to increase the effective inductor area without increasing the planar footprint, thereby maintaining high Q factor while reducing the occupied area on the substrate.
Solution Approach 2:
The patent employs composite material structures combining multiple metal layers (e.g., copper, aluminum) with different dielectric materials. This composite approach optimizes both the electrical properties (low resistance, high Q) and spatial efficiency by selecting materials with appropriate conductivity and insulation properties for specific functional layers.
2Reliability
If special metalization layers such as gold are used, then inductor Q is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the material parameter from expensive gold to cost-effective copper or aluminum, while compensating for the lower conductivity through optimized geometric parameters such as increased trace width, reduced trace length, and multi-layer stacking to achieve comparable or superior Q factor at lower cost.
Solution Approach 2:
The patent adopts inexpensive metal materials (copper, aluminum) that can be easily deposited using standard semiconductor manufacturing processes, replacing expensive specialty materials. The focus shifts to optimizing the structural design and fabrication process to achieve high performance with readily available, low-cost materials.
3Adaptability or versatility
If integrated passive devices are added to increase functionality, then device capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the fabrication processes for active devices and passive devices (resistors, capacitors, inductors) into a single integrated process flow. Multiple device types are formed simultaneously using shared process steps such as metal deposition, patterning, and etching, thereby increasing device capability while minimizing the increase in manufacturing complexity.
Solution Approach 2:
The patent designs a universal process platform that can fabricate various types of passive devices using the same base process steps. For example, the same metal deposition and patterning processes are used to create resistors, capacitors, and inductors, allowing the manufacturing system to produce multiple device types without requiring separate specialized process lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the production of high Q factor inductors with low insertion loss and capacitors in significantly reduced space, improving manufacturing yield and reducing costs while supporting the integration of high-quality analog circuits in wireless devices.
Implementation Method 1
depositing a metal capacitor layer on the first dielectric layer, and depositing a metal layer over the second dielectric layer
Data Source
AI summary
An integrated passive device system is disclosed including forming a first dielectric layer over a semiconductor substrate, depositing a metal capacitor layer on the first dielectric layer, forming a second dielectric layer over the metal capacitor layer, and depositing a metal layer over the second dielectric layer for forming the integrated capacitor, an integrated resistor, an integrated inductor, or a combination thereof.