Double-Sided IPD Package Layout for EMI and Coupling Reduction
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Solution Overview
Problem
Semiconductor devices face challenges in managing electromagnetic interference (EMI), radio frequency interference (RFI), and inter-device interference such as capacitive, inductive, or conductive coupling, which can interfere with their operation, especially in high-speed digital circuits, while simultaneously achieving higher performance, higher integration, and miniaturization.
Innovation Solution
The implementation of a semiconductor device with a double-sided integrated passive device (IPD) and a shielding frame to mitigate interference, using conductive materials like Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials, and optionally a heat sink to dissipate heat, while maintaining structural integrity and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If shielding is added to manage electromagnetic interference, then EMI/RFI protection is improved, but device complexity increases
Solution Approach 1:
The patent combines the shielding frame with the substrate structure, integrating the shielding function into the existing package substrate rather than adding it as a separate component. The conductive shielding frame is formed as part of the substrate assembly, merging structural support with electromagnetic interference protection functions.
Solution Approach 2:
The shielding frame serves multiple functions simultaneously: it provides electromagnetic shielding, acts as a ground reference, and contributes to the structural integrity of the package. The same conductive structure that forms the package substrate also provides the shielding function, eliminating the need for dedicated shielding components.
2Productivity
If double-sided IPD integration is implemented, then integration density is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent forms conductive pillars and shielding structures on the substrate before attaching the double-sided IPD. By preparing the conductive interconnect structures and shielding frame in advance on the substrate, the subsequent IPD attachment process is simplified, and alignment is facilitated.
Solution Approach 2:
The patent divides the interconnect structure into discrete conductive pillars that are formed separately and then used to attach the IPD. This segmentation allows for independent formation and testing of interconnect structures before final assembly, simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces EMI, RFI, and inter-device interference, enhancing the performance and integration of semiconductor devices while allowing for miniaturization and reducing manufacturing costs through streamlined processes.
Implementation Method 1
a conductive shielding frame is formed over a surface of the substrate. The conductive shielding frame may be formed of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials.
Implementation Method 2
and optionally a heat sink to dissipate heat
Data Source
AI summary
A semiconductor device has a semiconductor die, substrate, and plurality of first conductive pillars formed over the semiconductor die or substrate. Alternatively, the first conductive pillars formed over the semiconductor die and substrate. An electrical component is disposed over the semiconductor die. The electrical component can be a double-sided IPD. The semiconductor die and electrical component are disposed over the substrate. A shielding frame is disposed over the semiconductor die. A plurality of second conductive pillars is formed over a first surface of the electrical component. A plurality of third conductive pillars is formed over a second surface of the electrical component opposite the first surface of the electrical component. A bump cap can be formed over a distal end of the conductive pillars. The substrate has a cavity and the electrical component is disposed within the cavity. An underfill material is deposited between the semiconductor die and substrate.