Integrated Passive Device Package Structure for High-Density Substrate
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Solution Overview
Problem
Current high-density semiconductor packaging technologies face challenges in arranging and integrating passive components due to limited horizontal arrangement density and increased wiring distances, which hinder miniaturization and integration of package substrates.
Innovation Solution
A package structure for integrated passive devices involves vertically embedding electronic components within a substrate using an organic frame with chip embedding cavities and metal pillars, accompanied by dielectric layers and metal electroplating to form circuit layers, allowing for increased density and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If passive components are arranged horizontally in the PCB, then the components can be mounted and patterned, but the arrangement density per unit surface area is limited due to the large length and size of components
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical embedding of passive components in the PCB substrate. By utilizing the third dimension (depth/vertical direction), the component arrangement density per unit surface area is significantly increased without being constrained by the horizontal length and size of components. The vertical embedding allows components to be positioned within the substrate thickness rather than occupying surface area.
2Quantity of substance
If the number of components is increased to achieve high-density packaging, then the packaging capacity increases, but the wiring distance between components increases and manufacturing becomes more difficult
Solution Approach 1:
By embedding components vertically within the PCB substrate, the patent reduces the horizontal wiring distance between components. The vertical positioning allows for shorter interconnect paths through the substrate thickness, thereby decreasing the overall wiring length and improving signal integrity while accommodating a higher number of components.
3Quantity of substance
If passive components are embedded vertically in the substrate, then the arrangement density per unit area increases and wiring distance shortens, but the manufacturing process becomes more complex
Solution Approach 1:
The patent incorporates passive components during the PCB lamination process itself, rather than adding them in a separate post-processing step. The components are placed in cavities formed in the substrate layers before final lamination and curing, allowing the embedding to occur as part of the standard PCB manufacturing workflow. This preliminary integration reduces overall manufacturing complexity despite the vertical embedding requirement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces horizontal arrangement distances, enhances component density, and increases packaging capacity per unit area, enabling more efficient miniaturization and diversification of substrate functions.
Implementation Method 1
performing metal electroplating to form a circuit layer communicated with the upper electrode, the lower electrode and the metal pillar
Data Source
AI summary
Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar.