Integrated Passive Device Solder Interconnect for Thin GaNSiC Packaging
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Solution Overview
Problem
Current flip chip technology faces limitations in processing due to wafer size constraints and material properties of silicon carbide (SiC), particularly challenging for thin GaNSiC wafers, which restricts effective attachment and packaging.
Innovation Solution
The integration of a solder connection structure on an integrated passive device (IPD) chip, allowing for wafer-level packaging of GaNSiC semiconductor devices, enabling attachment of thin dies onto larger IPD wafers and reducing manufacturing costs through compatible bond pad metal stacks and wafer-level processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip chip technology is used to attach semiconductor devices, then connection reliability is improved, but wafer size is limited to 4 or 6 inches
Solution Approach 1:
The patent introduces an integrated passive device (IPD) as an intermediary carrier substrate between the semiconductor device and the final package. The IPD has a larger substrate area than traditional wafers, allowing semiconductor devices to be attached to the IPD first, and then the IPD itself is attached to the package. This intermediary approach enables wafer-level processing on larger areas without compromising connection reliability.
2Reliability
If thin GaNSiC wafers are processed with flip chip technology, then device performance is improved, but processing capability is limited due to material properties
Solution Approach 1:
The patent performs preliminary actions by attaching the thin GaNSiC semiconductor devices to the IPD carrier substrate before undergoing bumping and reflow processes. This preliminary attachment to a larger, more stable substrate provides mechanical support and thermal management during subsequent processing steps, making it feasible to process thin wafers that would otherwise be too fragile for direct flip chip processing.
3Ease of manufacture
If traditional packaging methods are used, then manufacturing process is simple, but assembly cost and complexity increase
Solution Approach 1:
The patent merges multiple functions into the IPD carrier substrate: it serves as the mounting platform for semiconductor devices, provides thermal management pathways, enables wafer-level bumping and reflow processing, and acts as an intermediate carrier during packaging. By combining these functions into a single integrated platform, the overall assembly process is simplified despite the advanced capabilities enabled.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances radio frequency (RF) and thermal performance while reducing assembly and manufacturing costs by enabling efficient attachment and packaging of thin GaNSiC dies on larger IPD wafers, improving product yield and scalability.
Implementation Method 1
The connection structure includes a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device
Data Source
AI summary
A device includes at least one integrated passive device having at least one bond pad; at least one semiconductor device having at least one bond pad; and at least one connection structure arranged on the at least one integrated passive device. Additionally, the at least one connection structure includes a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device.