Inter-Power Domain Timing Analysis Pruning
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Solution Overview
Problem
Multiple-voltage circuit designs require extensive testing to ensure timing synchronization, leading to increased runtime and memory usage due to the exponential growth of voltage combinations, with existing methods either missing potential timing violations or detecting false positives under inapplicable conditions.
Innovation Solution
The method involves identifying inter-power domain (IPD) timing paths and logic within a circuit design, allowing for selective multi-domain timing analysis by pruning the netlist to focus on IPD paths and logic, thereby reducing unnecessary testing while ensuring all applicable supply voltage conditions are checked.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comprehensive testing of all voltage combinations is performed, then timing violation detection reliability is improved, but runtime and memory usage increase exponentially
Solution Approach 1:
The patent segments the circuit design into multiple power domains based on voltage characteristics. By dividing the circuit into domains (e.g., high-voltage domain, low-voltage domain) and analyzing timing paths within and between domains separately, the exponential testing complexity is reduced to linear or polynomial complexity while maintaining detection reliability for inter-power domain timing violations.
Solution Approach 2:
The patent applies local quality by treating different power domains with different analysis approaches. Intra-power domain paths use standard timing analysis, while inter-power domain paths use specialized analysis that accounts for voltage transitions. This localized approach optimizes resource usage by applying comprehensive testing only where necessary (at power domain boundaries) rather than uniformly across the entire circuit.
2Reliability
If comprehensive testing of all voltage combinations is performed, then timing violation detection reliability is improved, but memory usage increases exponentially
Solution Approach 1:
The patent segments the circuit into power domains and processes timing analysis domain-by-domain rather than loading all voltage combinations into memory simultaneously. This segmentation enables streaming or iterative processing that reduces peak memory requirements from exponential to linear or polynomial in terms of circuit size.
Solution Approach 2:
The patent performs preliminary identification and classification of timing paths into intra-power domain and inter-power domain categories before detailed analysis. This preliminary action allows the system to prepare targeted analysis plans that minimize memory requirements by focusing computational resources only on critical inter-power domain paths rather than uniformly processing all paths under all voltage combinations.
3Reliability
If broader voltage ranges are tested, then timing violation detection coverage is improved, but false positive detections increase
Solution Approach 1:
The patent applies local quality by using specialized analysis methods tailored to different path types. Inter-power domain timing paths are analyzed with methods that specifically account for voltage domain transitions and level shifter behavior, while intra-power domain paths use standard timing analysis. This localized approach ensures comprehensive coverage of actual risk areas without applying overly conservative assumptions to paths where they are not needed, thereby reducing false positives.
Solution Approach 2:
The patent changes analysis parameters based on the specific characteristics of each timing path. For inter-power domain paths, the analysis incorporates voltage transition timing, level shifter delays, and domain boundary conditions. For intra-power domain paths, standard timing parameters are used. This parameter adaptation allows accurate detection without the false conservatism that arises from applying uniform broad-range testing to all paths.
Data Source
AI summary
A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.