3D Integrated Passive Device with TSV Vertical Stacking
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Solution Overview
Problem
The two-dimensional layout of integrated passive devices (IPDs) limits the capacity of capacitors and inductors formed within their substrates, making it difficult to provide necessary inductors and capacitors for applications requiring larger values, especially in semiconductor devices.
Innovation Solution
The method involves forming conductive Through-Silicon Vias (TSVs) through a substrate, creating a first IPD over one surface and a second IPD over an opposing surface, with the second IPD electrically connected to the TSVs, allowing for the formation of capacitors and inductors over opposing surfaces and enabling 3D interconnects to enhance integration and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors and inductors are formed within the IPD substrate using two-dimensional layout, then the IPD can be integrated, but the capacity of capacitors and inductors is limited
Solution Approach 1:
The patent transitions from two-dimensional planar layout to three-dimensional vertical stacking by forming capacitors and inductors on opposite surfaces of the IPD substrate. The first passive device (capacitor) is formed on the first surface, the substrate is thinned and patterned, and the second passive device (inductor) is formed on the second surface, enabling larger component capacities without increasing footprint area.
2Quantity of substance
If larger capacitors and inductors are provided, then system functionality is improved, but the IPD dimensions increase
Solution Approach 1:
By stacking passive devices vertically on opposite surfaces of the substrate rather than placing them side-by-side in two dimensions, the patent achieves larger capacitance and inductance values without increasing the IPD's footprint area. The vertical arrangement充分利用 the substrate's thickness dimension.
Solution Approach 2:
The patent nests multiple passive devices within a compact IPD structure by forming the first passive device on the first surface and the second passive device on the second surface, with both devices integrated within the same substrate volume. This nested arrangement maximizes component density.
3Adaptability or versatility
If more inductors and capacitors are integrated within the IPD, then device functionality is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the formation process into distinct stages: forming the first passive device on the first surface, thinning and patterning the substrate, and forming the second passive device on the second surface. This segmentation allows each manufacturing step to be optimized independently while maintaining overall integration.
Solution Approach 2:
The patent utilizes the substrate's thickness dimension to accommodate multiple passive devices, forming the first device on the first surface and the second device on the opposite second surface. This three-dimensional integration enhances device functionality without requiring proportionally more complex manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of larger capacitance values with a shorter connection path, minimizing IPD dimensions while maintaining system performance and providing more design capability, enabling more flexible and functional integrated circuits.
Implementation Method 1
forming a plurality of conductive TSVs through the substrate
Implementation Method 2
forming a capacitor over a first surface of the substrate
Implementation Method 3
forming a first conductive layer over a second surface of the substrate opposite the first surface of the substrate. The first conductive layer is wound to exhibit inductive properties
Data Source
AI summary
A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a surface of the IPD by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the resistive and dielectric layers. The first metal layer and the resistive layer are electrically connected to form a resistor and the first metal layer forms a first inductor. A wafer supporter is mounted over the IPD using an adhesive material and a third metal layer is deposited over the IPD. The third metal layer forms a second inductor that is electrically connected to the capacitor and the resistor by the TSVs of the IPD. An interconnect structure is connected to the IPD.